Technical Article

PCB Power Loop Layout for Chip-scale Package GaN FETs Optimizes Electrical and Thermal Performance

October 03, 2022 by John Glaser

In this article, different power loop layouts are analyzed with simultaneous considerations for thermal management and electric parasitics.

The results show that an improved layout can provide a significant reduction in operating temperature rise while maintaining electrical performance benefits.

Wide bandgap (WBG) power semiconductors like Gallium Nitride (GaN) have demonstrated better switching performance, high reliability and temperature capability with Figures of Merit (FOM) 3 to 10 times larger than comparable silicon devices [1]. GaN devices with small die size and on-resistance (RDS,on) reduce parasitic capacitance and inductance, increase switching speeds, and reduce switching losses allowing for much higher power densities and efficiencies. Higher frequencies would require some design attention to layout improvement to minimize added thermal resistance and inductance [2].


Existing PCB Layout Approach

The power loop layout considered in this article is the half-bridge configuration around which most power conversion layouts are built, comprising two power semiconductor switches and a bypass capacitor as shown in Figure 1. The inductor (l) averages the output voltage level of the switch node vSW = VLOW, and the capacitor CHF, while in theory not required since it is in parallel with VHIGH, is required in practice to provide a low impedance path for high-frequency currents.


Figure 1. Typical half-bridge building block. Parallel plate shorted transmission line (a). Half-bridge layout employing low-impedance transmission line as power loop structure with corresponding dimensions (b) and edge view of same (c). Image used courtesy of Bodo’s Power Systems [PDF]


The PCB design that minimizes power loop inductance, estimated by Lloop = µ0 · l · t/w, has been previously discussed [2]. Figure 1(b, c, d) shows a PCB implementation of the power loop. In summary, a PCB layout should minimize length and thickness while increasing the width w. This can be accomplished by the placement used in the layout of Figure 1(c), l and w are determined by the physical dimensions of the components, and t is set by voltage requirements or PCB manufacturability constraints.


The Buck Converter Thermal Challenge with Existing Layout

With the temperature of the switching devices becoming the limiting factor for electrical activation levels in many applications, improving heat dissipation has also become the main design consideration, especially at the PCB level, which plays a major part in removing heat from the FETs [3]. In a buck converter of Figure 1, Q1 is under a larger thermal load since it exhibits both switching and conduction losses, while Q2 only exhibits conduction loss. Figure 2 (Layout A) shows an exploded view of the standard layout of Fig. 1 (c). Thermally, the top layer has a higher resistance path for Q1, because of the interrupted copper plane by CHF. Q2, on the other hand, has a clear copper plane for heat to effectively spread into the PCB and eventually dissipate to ambient. Moreover, fewer vias are available for Q1 to avoid heavily perforating the GND return path. Therefore, Layout A is not thermally optimal for buck converter applications and an improved layout is needed to accommodate the higher losses without Q1 overheating.


Figure 2. Exploded view of power loop layouts with reference node and return path (GND) highlighted in green (Top). Top view of same with heat flow paths indicated by arrows (Bottom). Image used courtesy of Bodo’s Power Systems [PDF]


Considering a boost converter application on the other hand, the roles of Q1 and Q2 are reversed, with Q2 having the higher loss, in which case, Layout A performs well since Q2 has a lower thermal resistance.


Optimizing Layout for Buck Converter

As a rearrangement to thermally improve Layout A for buck operation, CHF can move to the side of Q2 since both are connected to GND (Layout B in Figure 2). This would require the use of layer 2 as a VHIGH plane, which still acts as an AC reference plane, and the dimensions l, w, and t are unchanged. Thermally, Q1 now has a good path to ambient and thus Layout B should perform better thermally under buck operation, but worse under boost operation since Q2 is now obstructed by CHF.


Eliminating the Tradeoff with a Capacitor-Centered Layout

For cases where a wide converter operating range, or bidirectional conversion is needed (Buck and Boost), Layout A or B are thermally restricted to one FET or the other. Moreover, in both layouts, Q1 and Q2 are closely placed and thus the heat generated is concentrated in a smaller area. These issues can be solved in Layout C by placing CHF in between Q1 and Q2. In Layout C, Q1 and Q2 are connected through the switch node (SW) in layer 2 shown in Figure 2. Layout C obeys the rules to minimize loop inductance, and while it is conventional to place the switch and signal nodes on the outer layer, it is not required for low impedance. The two nodes VHIGH and VLOW are at the same AC potential due to CHF and thus together form an AC reference plane and do not affect loop inductance.

The thermal benefits are that Layout C increases the spacing between and provides unobstructed copper planes for both Q1 and Q2. Also, there is more room for adjacent vias, the return plane is less perforated, and the switch node can be shielded by DC planes with potential EMI benefits.

Some possible drawbacks, not significant in practice, are that the farther spaced FETs may need a longer gate drive path when using a single package gate drive IC, and in some cases the capacitors may be taller than the FETs, which must be accommodated when mounting a heatsink.


Analysis and Verification

To test the above design proposals, hard-switched converters are used for their ease of design and well-understood behavior. The thermal performances of the three layouts design are compared in buck and boost operation. Identical boards with each power loop layout are designed and manufactured. The voltage VHIGH is selected at 150 V which is a typical value for the FETs used for Q1 and Q2. The conversion ratio is fixed at VLOW/VHIGH = 0.25, which implies that Q1 operates at a duty cycle of 0.25 and Q2 at 0.75. The dc inductor current is fixed at IL = 15 A, since this is near the saturation value of the inductor and a moderate value for the selected FETs. Thus, the converter processes 562W in all test cases. A switching frequency FSW = 100 kHz was chosen to give realistic FET power dissipation values. The above test parameters are the baseline for the conducted tests. Q1 is thermally overstressed in buck mode and Q2 in boost mode.


Figure 3. a) Loss simulation results, b) Switch node voltage vSW for buck converter Q1 turn-on transitions. Image used courtesy of Bodo’s Power Systems [PDF]


Electrical Simulation and Measurements

To estimate the heat dissipation in the FETs, electrical simulations were done in LTspice™ which included estimated PCB parasitics. FET losses were simulated as a function of set frequency, duty cycle, and temperature. Results are shown in Figure 3a.

The switching performance is measured to show the inductance difference between the different layouts. The switching waveforms presented in Figure 3b show the switch node voltage for the turn on of Q1 during buck operation. It can be seen that the three layouts show small differences in the ringing, indicating small effects on the parasitic inductance.


Thermal Testing Setup

Thermal testing is performed in a forced-air cooling test chamber with controlled airflow. Figure 4 shows the test connections and experimental setup. For thermal measurements, a 200 µm-wide hole is drilled through the PCBs in between the pads to provide access for an optical thermal sensor (OPSense® OTG-F sensor). This sensor is EMI immune and has an extremely small thermal mass.


Figure 4. a) Electrical Connections to motherboard and test PCB for thermal testing. b) Optical sensor measurement setup showing PCB drill holes for fiber optic sensor. Image used courtesy of Bodo’s Power Systems [PDF]


Thermal Simulation Model

Thermal simulations are performed using 6SigmaET [4], a commercial thermal and CFD software, to verify the measured observations. The PCB layouts are imported into the software with all the details required (copper conductors, vias, devices). Representative data points are used to validate with measurements.


Forced Air Convection Results

The first set of measurements is performed for the three layouts at 400 LFM air flow. From the thermal simulation results in buck and boost configuration given in Figure 3, the maximum temperature on the high side FETs shows that Layout A has a thermal advantage in boost, while Layout B is more effective in dissipating heat in buck mode.


Figure 5. Measurement (IR and fiber optic temperature sensor) and simulation results (surface temperature) for Layout C in boost. Image used courtesy of Bodo’s Power Systems [PDF]


Layout C, when compared to A and B, has similar (within 5%) or better thermal performance than A and B in their optimal operation mode (A in boost and B in buck mode) and a significant improvement over layouts A and B in their sub-optimal operation mode (A in buck mode and B in boost mode). Figure 6 presents the measured Q1 and Q2 temperatures in for the three layouts in buck and boost operation. The results show that there is no thermal penalty for layout C in bidirectional operation, whereas thermal performance is significantly lower for layout A in buck (10% higher temperature) and B in boost (25% higher temperature). Additional testing with heatsinks show a similar conclusion, with lower temperatures due to better cooling effectiveness and a larger spacing between Q1 and Q2 in Layout C [5].


Figure 6. Summary of Measurement Results and Temperature Rise Comparison for the three Layouts. Image used courtesy of Bodo’s Power Systems [PDF]



The three layouts A (CHF adjacent to Q1), B (CHF adjacent to Q2), and C ( between Q1 and Q2) show comparable electrical performance, with minor differences observed in the ringing frequency. Experiments support the supposition that under typical design conditions, Layout A is thermally optimized for boost converter operation and Layout B for buck operation. Layout A is thermally challenged under buck operation and Layout B under boost, showing a large thermal penalty (high peak temperature) if not operated in their optimal mode.

Layout C provides a large unobstructed copper plane and a larger spacing for Q1 and Q2 which improves overall thermal performance to what is at least equivalent and often better that Layouts A or B. Layout C is shown to be thermally viable for any operating condition and is particularly suited to wide range applications such as inverters, Class D amplifiers, and solar optimizers, as well as bidirectional applications such as battery interfaces with minimal drawbacks observed in testing.


This article originally appeared in Bodo’s Power Systems [PDF] magazine.

Featured image used courtesy of Adobe Stock