Packaging GaN in a TO247

With the introduction of the first 600V GaN transistor in a TO-247 package, designers can now attain even greater efficiencies and other system benefits for their power conversion applications.

 

TO-247 Package Benefits

Transphorm considered packaging a GaN transistor in an industry-standard TO-247 package based on the number of its desirable features for power applications:

• Good thermal conduction directly to a heat sink
• Accommodation of large die size for higher current and lower on-resistance devices
• Robust leads
• Minimal mechanical stress in mounting.

However, they also knew that along with these advantages come unavoidable package inductances that must be considered if the package is to be used with fast-switching devices. Since their GaN HEMTs are the fastest switching transistors available in the 600V range, the company posed the question: Can these GaN switches even be packaged in the TO-247? They have now answered this question in the affirmative with the introduction of a 63 mW, 600V, TPH3205WS GaN transistor (Figure 1). Recently announced during APEC 2015, engineering samples of the product are available now and full production scheduled for the end of Q2, 2015.

 

Figure 1: (a) TO-247 package (b) TPH3205WS internal cascode configuration

 

GaN HEMT Specifications

Before describing the details of the device, it is helpful to consider the benefits desired in the target applications and the performance characteristics that are required from the switching device to achieve those benefits. We’ll consider one of Transphorm’s primary goals, which was to improve performance in applications that require continuous inductor current in alternating directions, such as inverters or bridgeless totem-pole, power-factor correction circuits.

The basic building block for such circuits is a simple two-transistor half-bridge. Assume a half-bridge is desired to convert 2.5kW of power at a switching frequency of at least 100kHz with a peak efficiency of 99% at half load. A typical partitioning of the losses might be 65% for the semiconductors and 35% for the magnetics. That would allocate 8.1W as the loss for the two transistors (65% of 1% of 1250W).

For optimized transistors this loss would further divide evenly between conduction loss and switching loss. In practice, the optimization point, where conduction loss equals switching loss, will likely be higher than half load due to full-load thermal considerations. If we partition the 8.1W loss at half load as 5.5W switching loss and 2.6W conduction loss and then divide 5.5W by 100kHz, we get a target energy loss per switching cycle of 55mJ. The exact partitioning of losses depends on the circuit detail, but this gives an idea of what is needed and will help determine just how fast the switch needs turn on and off.

Detailed loss analysis of GaN cascode switches has been provided in several helpful references, such as the papers [1]-[3] referenced at the end of this article. For our purposes in this article, a relatively simple approach will suffice to indicate if the device is compatible with the objectives. The key parameters for the TPH3205WS are provided in Table 1. 

 

Table 1: Parameters from the TPH3205WS preliminary datasheet

 

At turn-off, energy E_OSS is stored on the output capacitance of the switched transistor. This energy will be dissipated at turn-on. Also at turn-on, the output capacitance of the freewheeling transistor will be charged through the active switch. For a linear capacitance, this would result in dissipation of the same energy, E_OSS . Because Coss is nonlinear, slightly more energy (about 2E_OSS) is dissipated in the charging process. Additional loss occurs during the finite time needed

for the drain current of the active switch to increase to the value of the inductor current, which is roughly (but not exactly) the turn-on delay time. This part of the turn-on loss is approximately

 

The reverse-recovery charge, Qrr, of the transistor carrying the free-wheeling current also contributes to loss. For the cascode GaN HEMT, most of Qrr is charge stored on the output capacitance, and therefore already included in the E_OSS term. The small amount of injected charge in the body diode of the silicon FET is removed by the switched transistor and contributes loss

 

Injected charge is proportional to load current:

 

where t has units of time and is on the order of 1ns. The total switching energy per cycle is

 

Given E_OSS = 15mJ from the datasheet and assuming Vdd=400V and IL-ave=5A (corresponding to 1250W/230Vac), a turn-on delay time of 8ns will suffice to achieve the desired Esw of 55mJ. Note that in table 1 the TPH3205WS has a specified turn-on delay of 7.2ns. The analysis given here is approximate, but serves to indicate the speed required for this application. Figure 2 shows the Vds turn-on waveforms relevant to the preceding discussion (although at a higher inductor current, IL=19A).

 

Figure 2. Half-bridge switching waveforms. Simulated Vds and Id (a) and oscilloscope Vds and IL (b)

 

Test Results

To show what has actually been achieved with the TPH3205WS transistor, Tranphorm conducted tests for two applicaiton circuits - a totem-pole PFC and a single-phase inverter.

 

Figure 3: Totem-pole PFC simplified schematic (a) and evaluation PCB (b)

 

The bridgeless totem-pole PFC [4] has received much attention in recent years as a simple, high-efficiency topology. Figure 3 shows a simplified schematic of this topology was tested and a photo of the TPH3205WS used on 2.4kW evaluation board that tested by Transphorm. S1 and S2 on the board are the GaN transistors, which are mounted back-to-back on the heat sink. SD1 and SD2 are silicon MOSFETS, which are switched at line frequency (60Hz) and incur only a small conduction loss. The DC output voltage is 385Vdc. The heat sink is sized to permit operation without forced-air cooling. Test results are shown in Figure 4.

 

Figure 4: Totem-pole PFC efficiency and loss at low line (115Vac) and high line (230Vac)

 

A 3kW, full-bridge single-phase inverter was also built by Transphorm and tested using the TPH3205WS. Figure 5 shows the simplified schematic and PCB assembly for this circuit. Measured efficiency for this circuit is provided in Figure 6. Consistent with our preliminary analysis, which counted switching loss in a single half bridge, this inverter was operated in a unipolar switching mode. Bipolar switching would lower the efficiency by adding switching loss of the second half bridge.

 

Figure 5: Single-phase inverter simplified schematic (a) and evaluation PCB (b).

 

As can be seen in the above graphs, the efficiencies peak quite close to the 99% target. The differences can be accounted for by more exact analysis of the transistors themselves, and by inclusion of additional loss factors in the circuit.

At higher switched current levels, ringing of parasitic inductances does increase and use of RC snubbers can be considered. The efficiency data presented here was in fact from boards which included 8W/44pF snubbers across each transistor. These were not strictly necessary for the power level tested, but it is significant to note that the associated loss is included in the results shown.

 

Figure 6: Single-phase inverter efficiency and loss

 

Conclusion

In spite of the inductances that must be considered with a TO-247, it nevertheless has proven to be a robust package that brings the benefits of GaN technology in an immediately accessible form. By now offering a 600V GaN HEMT in this industry-standard package, GaN transistors can be extended to a wide range of applications, including PV inverter designs with power levels ranging from a few 100 watts (micro-inverters) to several kilowatts (residential central inverters).

 

About Transphorm

Transphorm is a global semiconductor company that develops gallium nitride (GaN) transistors and modules for high-voltage power conversion applications. Built on an industry-leading IP portfolio and over 300 years of combined GaN engineering expertise, Transphorm is delivering the highest performance and highest reliability GaN devices and best-in-class applications-driven design support to a growing customer base.

 

References

1. X. Huang, Q. Li, Z. Liu, and F. C. Lee, “Analytical loss model of high voltage GaN HEMT in cascode configuration,” IEEE Transactions on Power Electronics, vol. 29 (5), 2208-2219, May 2014
2. X. Huang, Z. Liu, F. C. Lee, and Q. Li, “Characterization and Enhancement of High-Voltage Cascode GaN Devices”, IEEE Transactions on Electron Devices, vol. 62, no. 2, February 2015
3. Z. Liu, X. Huang, F. C. Lee, and Q. Li, “Package parasitic inductance extraction and simulation model development for the high-voltage cascode GaN HEMT,” IEEE Transactions on Power Electronics, vol. 29, issue 4, pp.1977-1985, April. 2014
4. L. Zhou, Y. Wu and U. Mishra, “True Bridgeless Totem-pole PFC based on GaN HEMTs”, PCIM Europe 2013, 14-16 May, 2013, pp.1017-1022.