Dynamic ON-Resistance Measurement Techniques for GaN Power Transistors
Dynamic on-state resistance is critical for the reliable and stable operation of GaN power transistors. However, many engineers are struggling to evaluate dynamic RDS(ON) because of the difficulty in measuring it consistently with sufficient resolution. In this article, we discuss a measurement technique of dynamic RDS(ON) using a double pulse test system with a clamp circuit
“Current Collapse” Behavior of GaN Power Transistors
While GaN power transistors are becoming popular in power electronics applications because of their low energy loss and high power density capability, design engineers still have some concerns about their reliability. One of the key concerns about GaN power transistors is their dynamic on-state resistance (RDS(ON)) increase during switching operation, the phenomenon known as “current collapse”. Current collapse is the result of trapped electrons in the transistor structure when a high drain off-voltage is applied. It takes time to clear out the trapped electrons during a switch-on event, which is characterized by the dynamic RDS(ON) measurement. Increased dynamic RDS(ON) degrades conduction loss of the GaN power transistors and leads to higher temperature, which affects the reliability of the GaN power transistor and the system overall. Although many manufacturers provide “collapse-free” GaN power transistors, engineers are still concerned about the effect of the current collapse. Therefore, not only device manufacturers but also power converter design engineers need to evaluate dynamic RDS(ON) of GaN power transistors accurately.
Challenges for Dynamic ON-state Resistance
measurement Many engineers are struggling to evaluate dynamic RDS(ON) accurately. There are two main reasons: 1) overdriving, and 2) the limitation in the oscilloscopes’ dynamic range.
When we measure dynamic RDS(ON), we would like to set the oscilloscope range just enough to monitor only on-state drain voltage (VDS(ON)) such as 1V/div, giving us the best resolution from the oscilloscope. Unfortunately, the transistor is switching from high drain off-voltage (VDS(OFF)) such as 400 V. The amplifiers in the oscilloscope distort the waveform if the measurement range is not wide enough to cover both VDS(OFF) and VDS(ON). This phenomenon is called “overdriving” of the oscilloscope  and results in saturated oscilloscope amplifiers and erroneous VDS(ON) measurements.
Therefore, we must set the oscilloscope range wide enough to capture both VDS(OFF) and VDS(ON) to avoid overdriving the input. However, the issue we come across this time is the limitation in the dynamic range of oscilloscopes. Even the high-end oscilloscopes, which have the highest vertical resolution in the market only have around nine effective number of bits (ENOB) at 20 MHz bandwidth (NOTE: In most cases, ENOB is the more useful parameter to use than the raw number of bits of the ADC in the oscilloscope. Often a few of the raw bits are below the noise floor of the amplifier, making them unusable). Therefore, the oscilloscope can only identify 1/29 = 1/512 of full scale. If VDS(OFF) is 400 V, the minimum resolution will be 400/512 = 0.78 V, which is completely unacceptable resolution for dynamic RDS(ON) measurements.
Keysight's Approach to Measure Dynamic RDS(ON)
To overcome this and other challenges in testing GaN power transistors, Keysight developed a customized GaN test board to use with the PD1500A Dynamic Power Device Analyzer and Double Pulse Tester. To specifically overcome the limitation of the oscilloscope dynamic range, we developed a clamp circuit. Figure 1 shows our customized GaN test board. The newly developed clamp circuit is placed near the interface of the device under test (DUT). As we discussed in previous articles, the board also has Keysight’s solderless DUT interface, low insertion inductance current sensor, and replaceable gate resistors that we call Repeatable & Reliable GaN Characterization (R2GC) Technologies.
Figure 1. Keysight’s customized GaN test board with R2GC technology.
Figure 2 shows a simplified concept of the clamp circuit. This circuit is placed in parallel to the output of the DUT. For example, assume the voltage threshold (VTH) of Q1 is 2 V. If the Clamp Voltage is set to 8 V, then this circuit accurately measures the voltage VCLAMP up to 6 V when the VDS of the DUT is below 6 V. However, when VDS is above 6 V, then the system measures no more than 6 V. This means the oscilloscope can be set at a low-voltage range such as 1 V/div, which gives enough vertical resolution for dynamic RDS(ON) measurements. This test method using a clamp circuit is also suggested in JEDEC’s publication JEP173 .
Figure 2. Simplified example of the clamp circuit.
Figure 3. Turn-on switching waveform of a 650 V rating GaN E-HEMT obtained by the newly developed GaN test board with a clamped circuit.
We evaluated the performance of our customized GaN test board with a commercially available 650 V rating GaN E-HEMT (Enhancement mode High Electron Mobility Transistor). Figure 3 shows the turn-on waveforms of the GaN E-HEMT switching at VDS(OFF) = 400 V, IDS(ON) = 30 A. The yellow waveform shows clamped drain voltage (VCLAMP) and the brown line shows RDS(ON) calculated by VCLAMP/IDS, using a 20 MHz low pass filter setting on the oscilloscope. The yellow waveform shows that the measured VDS is clamped at around 4.5 V and that VDS(ON) around 2 V is clearly measured. Peak-to-peak noise of RDS(ON) waveform was around 1 mW (30 mV in terms of VDS(ON)), which is much more precise than the original VDS resolution of 0.78 V we discussed above and sufficient to evaluate dynamic RDS(ON) for most GaN power transistors.
Figure 4. Measurement result of 100 V/10 mW GaN E-HEMT dynamic RDS(ON) obtained by both PD1500A (with the newly developed clamp circuit) and B1505A
Another important characteristic for the clamp circuit is response time of the circuit. In typical power electronics applications like DC-DC converters, the switching frequency of the GaN power transistors is getting faster and faster and has become more than 1 MHz. That means the response time of the clamp circuit should be less than a few hundreds of nanoseconds to measure the dynamic RDS(ON) under practical operating conditions. The components of the clamp circuit like transistors and diodes intrinsically have a certain amount of junction capacitance and recovery characteristics that degrade the response time of the circuit. Therefore, getting fast response of the clamp circuit is another challenge.
Getting back to Figure 3, the clamped VDS waveform (yellow) shows a negative dip for about 50 ns just after the turn on transition starts. This negative dip is attributed to the effect of parasitics of the clamp circuit. After this dip, the clamped VDS shows correct VDS(ON) waveform. The response time of the clamp circuit in our double pulse test system proved to be less than 100 ns, which is fast enough for most applications.
We also compared our new dynamic RDS(ON) test method with our previous system (B1505A with N1267A HVSMU/HCSMU fast switch). Figure 4 shows the measurement result of 100 V/10 mW GaN E-HEMT obtained by both systems. Since B1505A is based on source measure unit (SMU) technology, it takes the measurement tens of microsecond to settle. On the other hand, PD1500A’s clamp circuit has approximately 1000 times faster response time and successfully detects the fast response of the current collapse behavior which occurs within 100 ns from turn-on. The result also shows that the noise floor of the measured dynamic RDS(ON) is roughly ten times smaller than B1505A, proving that we did a significant improvement in the dynamic RDS(ON) measurement
To explore more about our dynamic RDS(ON) test capability, we evaluated Off pulse length and VDS(OFF) dependency of the dynamic RDS(ON) for a 650 V rating GaN E-HEMT. In general, the dynamic RDS(ON) of GaN power transistors which have current collapse increases when longer and higher VDS(OFF) stress is applied. The effect of the current collapse can be seen by comparing RDS(ON) between the first pulse and the second pulse of double pulse test waveform.
Figure 5 shows the dynamic RDS(ON) behavior of the GaN E-HEMT during double pulse test. We extracted the deviation of RDS(ON) (ΔRDS(ON)) between 1st pulse (100 ns before VGS turns off) and 2nd pulse (100 ns after VGS turns on). As shown in Figure 6, ΔRDS(ON) slightly increased as longer and higher VDS(OFF) stress was applied, confirming that our double pulse test system can evaluate the current collapse of GaN power transistors effectively.
Figure 5. Dynamic RDS(ON) double pulse test result and ΔRDS(ON) extraction of a 650 V rating GaN E-HEMT at 500 V/20 A.
Figure 6. Off pulse length and VDS(OFF) dependency of ΔRDS(ON) for a 650V rating GaN E-HEMT
Current collapse is still one of the biggest concerns over GaN power transistors for many engineers, and its evaluation is very challenging due to the limitation of test instruments. As we discussed in this article, we successfully created a repeatable and reliable double pulse test system that can effectively evaluate dynamic RDS(ON) of GaN power transistors by employing a newly developed clamp circuit.
1. “Overcoming Overdrive Recovery on High-Speed Digital Storage Oscilloscopes” Application Note 5989-0068EN, Keysight Technologies
2. “Dynamic ON-Resistance Test Method Guidelines for GaN HEMT based Power Conversion Devices,” Version 1.0, JEP173.
This article was co-authored by Takamasa Arai, Keysight Solution Application Engineer, Ryo Takeda, Keysight Solution Architect, Bernhard Holzinger, Keysight Technical Architect, Michael Zimmerman, Keysight R&D Engineer, and Mike Hawes, Keysight Power Solution Consultant.
This article originally appeared in Bodo's Power Systems Magazine.
Nice article with good explanations and waveforms. The fast clamp circuit capable of 50 ns settling time provides good performance insight at delay times much shorter than previous methods. Just a minor point about the difference between dynamic Rds(on) versus current-collapse: In figure 5 you show the second pulse has a higher initial dynamic Rds(on) than the first pulse. This is due to charge that gets trapped in the time between the first and second pulses as you say. But as long as the Dynamic Rds(on) is decreasing, asymptoting to the DC value when the HEMT is ON, this is not current-collapse, its simply dynamic Rds(on) which has changed due to precondition. Current-collapse is when the slope of dynamic Rds(on) becomes positive. This usually does not end well - the slope will exponentially increase until the HEMT can no longer sustain the load current, and Vds then rises all the way back to the bus, while the transistor is still conducting significant current. The transistor can only survive this huge dissipation for a short time before thermal destruction occurs.