Technical Article

Achieving very low or zero standby power for AC-DC power supplies

March 30, 2016 by Florian Mueller

In the future, the average household will have more than 60 devices plugged in and on standby 24 hours a day. From coffee machines and TVs to chargers

In the future, the average household will have more than 60 devices plugged in and on standby 24 hours a day. From coffee machines and TVs to chargers and smart plugs, these devices can cost households hundreds, even if inactive. But while consumer demand for electrical goods increases, global energy standards are driving the need for reduced standby loss.

For example, the European Commission Code of Conduct (COC) and the US Department of Energy (DOE) define standby power standards for power supplies when they are on, but disconnected from a load. The COC limits the no-load power consumption for 1W to 49W output power rating to 75mW (Tier 2) and the DOE to 100mW. The Energy Star program, developed in the US and expanded to the EU, for cell phone charger limits the no-load power to 30mW for the highest 5 stars. However, the industry is pushing even for less than 5mW standby power which is called zero standby power.


Flyback Topology

At low power levels, the flyback topology is probably the best choice for an offline design. It is one of the least expensive isolated topologies because it uses a very low number of components. In the past, an optocoupler was normally  used to regulate the secondary side output but modern quasi-resonant (QR) flyback controllers provide primary side regulation, enabling designers to bypass the optocoupler altogether.

Primary side regulation uses magnetic feedback via the bias winding to close the feedback loop. This makes it among the most cost-effective isolated offline topologies because a simple resistor divider connected to the bias winding is sufficient to regulate the output voltage. This article focuses on achieving low standby power for a primary-side regulated QR flyback.


Primary-Side Regulated Flyback

Figure 1: Primary-Side Regulated Flyback
Figure 1: Primary-Side Regulated Flyback


Figure 1 shows the schematic of a PS QR flyback controller (UCC28710) from Texas Instruments. The quasi-resonant operation uses the resonance ringing, caused by the circuit parasitics and the primary inductance, to lower the switching losses (see Figure 2: Switch node Voltage).

After the core of the transformer is completely demagnetized (secondary side current has ramped down to zero) there will be a resonant ringing, caused by the primary inductance and the energy stored in the parasitic switch node capacitance. The controller detects the valley of the resonant ringing and turns on the MOSFET. The switching frequency varies in order to have the switching event happen in a valley. The lower switch node voltage at the valley reduces switching losses.


Figure 2: Switchnode Voltage (drain-to-source voltage of the primary MOSFET)
Figure 2: Switch node Voltage (drain-to-source voltage of the primary MOSFET)


Components of Standby Power

The total standby power consists of two main components.

  1. Energy, which is taken every switching cycle from the input.
  2. The loss of the startup circuit.

The leakage losses of the input bridge rectifier and the bulk capacitors have also a contribution to the total loss, but they are very small (usually below 1mW even for an input voltage of 230VAC) and must only be considered for achieving zero standby power.

The parasitic switch node capacitance and the snubber network also add additional losses to standby power.


Minimum Cycle Energy

The controller takes a minimum amount of energy from the input each switching cycle, called the minimum cycle energy. The two limiting factors for the lowest possible minimum cycle energy are the minimum controllable on-time ton_min and the minimum switching frequency fsw_min. ton_min cannot be affected by the designer. This time is mainly determined by the leading edge blanking time and is given in the datasheet. On the contrary, fsw_min can be chosen by the designer. Usually, the minimum possible switching frequency of the controller or the required transient response defines fsw_min. Unfortunately, there is a trade-off between low standby power and fast transient response. The lower the fsw_min, the lower the standby power, but this has a negative impact on the transient response.

Why is this the case? A primary side regulator does not monitor the output voltage constantly. The controller samples the auxiliary voltage just one time per switching cycle to control the output voltage. During the rest of the period time, the controller is blind. It can take up to the period of time to detect a load transient, meaning the transient response is worse for longer period times, and respectively for lower switching frequencies.


Startup Circuit

There is a resistive startup method, which results in a high increase in standby power because the startup resistor is permanently connected to the very high bulk voltage VBLK, allowing power to dissipate in the resistor. For low standby power applications, an active startup method must be used, as the controller UCC28710 (see Figure 1). The principle is simple, a normally on a device, usually, a depletion mode FET, replaces the startup resistor. Once the output voltage ramped up, the controller can turn off the startup FET. This reduces the losses in the startup circuit significantly.


TVS Snubber Network

For a low standby power application, it is better to use a TVS snubber instead of an RCD (resistor, capacitor, diode) snubber. While the TVS snubber is more expensive, it achieves higher efficiency because the power is not dissipated before the TVS cathode voltage reaches Vin+Vclamp.

The choice of the correct diode is also very important - an ultra-fast diode is important if a TVS snubber is used for a valley switching topology. In some low power applications, it is possible to disclaim the snubber network. This will decrease the standby power further.


Parasitic Switch Node Capacitance

The parasitic switch node capacitance CSN has also an impact on the standby power. CSN is the sum of the parasitic capacitances of the MOSFET (Coss), the transformer, snubber diode, output diode, and the layout. The dominant part is the MOSFET output capacitance Coss. Each switching cycle the energy EIN_PAR (EIN_PAR = CSN*VBULK2 ) is stored in CSN. A portion of this energy is dissipated in the switch and in the snubber. The remaining energy is delivered to the auxiliary and secondary outputs. Decreasing CSN is helpful to achieve very low standby power.


Minimum Load Requirement

If the cycle energy is not absorbed then the output voltage loses regulation and increases if the output is unloaded. This is prevented by applying a minimum load on the output, usually in form of a resistor. In fact, a bigger pre-load improves the transient response but increases the standby power. If the secondary side parts withstand a higher output voltage then a very low minimum load can be used which lowers the standby power.


Zero Standby Power

Achieving zero standby power is very tough. The losses without an active load must be less than 5mW across the input voltage range. The switching frequency must be reduced dramatically to achieve this low power level. Unfortunately reducing the switching frequency has a big tradeoff. The transient response gets very bad because it can take up to the period of time before the controller detects an output voltage drop.  Texas Instruments found a solution to this problem.

There is a zero standby power chipset, consisting of a primary side regulated flyback controller (UCC28730) and a wake-up controller (UCC24650). The UCC28730 operates with a very low switching frequency of the only 32Hz under no output load conditions. The UCC24650 monitors the output voltage Vout constantly. If Vout drops more than 3% due to a load step, the wake-up controller sends a wake-up signal to the primary side through the transformer (across the isolation barrier). There is no need for an additional isolation component. The primary side controller (UCC28730) detects the wake-up signal and increases the switching frequency immediately by delivering three transition-mode pulses. This approach enables a fast transient response and a very low standby power at the same time.


Industry's first zero standby power PSR solution


It needs some effort to achieve very low standby power. Many components make up the final result- from an active start-up circuit and a small switch node capacitance to low switching frequency. Fortunately, a primary side controlled topology does not have to deal with losses of an optocoupler and an external error amplifier. Nevertheless achieving zero standby power is difficult, even for a primary side regulated controller. A smart method, like a wake-up controller, is needed to limit the standby losses to less than 5mW for high-power AC/DC power supplies – minimizing energy and financial waste for example when your phone charger is left plugged in all day.


About the author

Florian Mueller was born in Rosenheim, Germany, in 1976. He received a degree in electrical engineering from the University of Haag. After working for several years as a freelancer in the field of electrical engineering, he joined TI in 2008 and is working in the European Power Design Services Group, based in Freising, Germany. His design activity includes isolated and non-isolated DC/DC and AC/DC converters for all application segments.


This article originally appeared in the Bodo’s Power Systems magazine.