Tech Insights

Could GAAFETs Replace FinFETs?

November 06, 2020 by Lorenzo Mari

A look at how GAAFETs could replace FinFETs as the technology of choice to keep down size and provide extremely high density for power devices.

The metal-oxide-semiconductor field-effect transistor (MOSFET) may be the most remarkable electronics achievement of the 20th Century. The first commercial MOSFET circuits appeared in 1964 and became very popular because of their high packing density, small power consumption, and low cost.

Integrated circuits were introduced in 1958 and complementary MOS (CMOS) technology in 1967. The first commercially produced microprocessor was the Intel 4004, released by Intel Corporation, in 1971. It started a race for miniaturization and performance improvements.

Gordon Moore’s prediction — known as Moore’s law (1965) — started an industry roadmap with exponential profits. The semiconductor industry has come to be one of the largest, with CMOS technology making impressive advances.

Not long ago, transistors were planar. They were large enough to disregard the problems arising from having a small gate, such as the leakage current.


Planar MOSFET (1 gate)
Planar MOSFET (1 gate)


As manufacturing processes advanced, the transistors, and the gates, kept getting smaller and less effective. Scaling brought numerous new issues. Short channel effects, variability, quantum tunneling leakage, and mobility degradation presented crucial difficulties as the device dimensions lessened.

One way of resolving these issues was to evolve to a three-dimensional configuration, with the channel’s gate on three sides, giving it more surface area to control the electrostatics. The engineers considered multi-gate devices such as the Fin-shaped FET, bringing to life what we know as the FinFET transistor.


FinFET (3 gates)
FinFET (3 gates)


This method had many benefits — less leakage current, enhanced drive current, faster switching time, and superior scalability — improving the channel’s control while reducing the transistor’s overall size. The gate surface could be maintained or increased — the leakage current and other short-channel problems were back under control.

When the technology evolved from 22nm to 16nm, many semiconductor fabrication companies changed from planar to FinFET transistors.

Intel showed a 22nm wafer at the Intel Developer Forum on September 22, 2009. The size of the cell was the smallest SRAM at the time. Intel used its 3D Tri-Gate process for the first time ever. 

But the FinFET is also limited, and it has shown signs of exhaustion in the last two generations. At the 3nm process node and beyond, FinFETs may no longer control the leakage current and other short-channel effects properly, requiring new technologies to continue the scaling one further step.

The latest node technologies, employing FinFETs, have seen a slowdown in the cost reduction rate. This fact has lowered the number of companies having advanced node technologies in mass production.

Now, the industry’s semiconductor companies and foundries face a new transistor revolution.


A Transistor Evolution

FinFET is a technology with an expiration date. Post-FinFET transistor research — over the last decade — is assessing an evolution from a gate that surrounds three sides of the channel to a gate that entirely encloses it (similar to a cylindrical channel encircled by a tube-like gate). This arrangement is the Gate-All-Around FET or GAAFET with nanowires or nanosheets. This design is more involved to build than FinFETs or planar transistors. Nanowires and nanosheets technologies are currently in progress, raising the channel and allowing its width to scale as needed.


GAAFET (4 gates – nanosheets)
GAAFET (4 gates – nanosheets)
GAAFET (4 gates – nanowires)
GAAFET (4 gates – nanowires)


Samsung took the first step to position itself as a leader presenting the Multi-Bridge Channel FET or MBCFET technology at its 3nm manufacturing process. This technology integrates new gate-all-around transistors as the main innovation.

The new Samsung’s transistors are nanosheets. The stacking is vertical, with horizontal nanosheets, like a stack of printer paper, replacing the traditional fins.

When compared to FinFETs, Samsung highlights three advantages:

  1. No need for an extra area to improve speed. Nanosheets are stacked vertically instead of adding parallel fins.

  2. It is expected that MBCFETs will be able to replace FinFETs without changing the size or configuration of a device's footprint.

  3. Supports the same process tools and manufacturing methodology as FinFET, reducing costs, and accelerating the implementation.


With GAAFET transistors still in the testing phase, we cannot declare final performance or efficiency improvements. Samsung estimates that at the same lithographic process of 3nm, the figures are 50% power savings, 30% performance improvement, and 45% area reduction.

These high figures will undoubtedly mark a before and after in the chips that implement it. Looking back to the jump from planar to FinFET, we could say that these numbers are credible.

Samsung’s initial schedule was to reach volume production by 2021, reaching the market by 2022. However, they recently announced some delays resulting from the COVID-19 crisis.

Other semiconductor manufacturers such as Intel or TSMC have not yet officially spoken. Still, it is expected that they will make their announcements about this technology sooner rather than later.

Intel is still designing with FinFETs by increasing the fin’s height. However, someday the capability to scale a FinFET will be unaffordable, and eventually the need to use new technologies to maintain scaling will become imminent.

An Intel spokesperson recently gave a clue,  indicating that they expect to produce GAAFETs in no more than five years.  

TSMC will stay on FinFET for the 3nm process technology. They acknowledge their ability to update the FinFETs to allow scaling through another iteration of the process node. TSMC is also taking advantage of the predictability of FinFETs to comply with their approved timescale.

TSMC, Intel, and Samsung will all look to maintain leadership status for the best 3nm and 5nm lithographic processes.


The Future of FETs

The popularity of mobile devices made possible by the VLSI circuits — cramming billions of transistors in a minimal area — joined the needs of boosting computational power and energy efficiency.

The always-on-standby devices such as smartphones, augmented and virtual reality (AR / VR), and the Internet of Things (IoT) require ultra-low-power systems, keeping the industry searching for better transistors.

Many substitutes for CMOS transistors are being researched. Adding gates to produce gate-all-around transistors might be the final solution to control electrostatics in ultra-scaled channels. The choice of vertically stacking channels could be the maximum of conventional CMOS scaling.

It will be exciting to discover who takes the lead in a competition no longer for the node’s density and performance, but area reduction and energy consumption.