The Challenges of Using SiC MOSFETBased Power Modules for Solar Inverters

This article examines SiC MOSFETs as a viable option for meeting the rising demand for faster switching and greater efficiency in 1500 V solar applications. It looks at their benefits – SiC MOSFETs enable deeper integration and greater power density – and their drawbacks in terms of switching performance. The intrinsic properties of the latest generation of devices appear to inhibit performance and reliability. This article analyzes the root cause of these limitations and proposes solutions to overcome them.

 

Advanced Neutral Point Clamped (ANPC) Solar Inverter

The object of investigation is an ANPC (active neutral point clamped) power module equipped with Si IGBTs and SiC MOSFETs as bare die. This ANPC is an improved version of the three-level NPC inverter topology. Figure 1 depicts an ANPC schematic with four grid-frequency synchronized IGBTs (T1-T4), their anti-parallel diodes (D1-D4), and two fast-switching MOSFETs (T5 and T6). The target application is a 1500 V string inverter with high switching frequency (up to 64 kHz) and high efficiency. Figure 1 shows one phase out of the three-phase inverter system, including the power module, dc-link capacitors (CDC1 and CDC2) and inverter choke (LAC).

 

Figure 1: Active neutral point clamped (ANPC)

The switching performance of various suppliers’ SiC MOSFETs was investigated in a hard-switching, totem-pole half-bridge configuration. All measurements were taken at a double-pulse characterization test station with a power module as shown in figure 1. The same DCB layout was used for all three measurements to ensure the parasitic inductance attributable to the layout, wire bonding and distance between pins would not affect the results. The only variable was the investigated type of SiC MOSFET. This characterization test station’s low-inductive drive circuit supports positive and negative multiple-ampere gate drive currents. One SiC MOSFET was selected as an example for the in-depth investigation conducted for this paper.

The double-pulse measurement assessed the low-side MOSFET T6’s switching waveform and switching energies. This MOSFET formed a commutation pair with the body-diode of the high-side MOSFET T5. T6 stayed on for a prolonged period to build up current, and was then switched off for a short time to allow the current to commutate fully in the body-diode of the opposite MOSFET T5. Then the low-side MOSFET T6 was turned ON again and the MOSFET and diode’s switching waveforms and energies were measured at that moment.

 

Double-pulse measurement result

The turn-ON waveform of the low-side MOSFET T6 shown in figure 2 indicates a sharp spike of the drain current followed by ringing of the drain current and gate voltage. This indicates a parasitic turn-ON of the opposite device, also called cross-conduction or shoot-through.

 

Figure 2: Cross-conduction at low-side SiC MOSFET turn-ON, Uds: light blue, Ids: dark blue, Ugs: yellow (Udc=600 V, Ids=140 A, Tj=150 C, Vg=-5/16 V)

 

Explanation of the root cause

Before the low-side MOSFET T6 turns ON, the current is freewheeling in the body diode of the high-side MOSFET T5. During turn-on, the current commutates from the high-side diode to the low-side channel (figure 3). This causes the diode to block and the voltage potential of the midpoint to change with high dv/dt from DC+ to 0 V.

Figure 4 shows the position of the SiC MOSFET’s intrinsic capacitances. The Miller capacitance Cgd is located between drain and gate, while Cgs is between the gate and source, and Cds is between the drain and source.

 

Figure 3: The current path in hard-switched ANPC

The voltage across Cds increases with high dv/dt. The current then flows through Cgd and Cgs. The voltage on Cgs rises. If it reaches the turn-ON threshold, the MOSFET starts conducting current in its channel.

 

Figure 4: The SiC MOSFET’s internal device capacitances and gate resistance

 

This renewed turn-ON causes the current spike in the low-side MOSFET’s drain shown in figure 2, and therefore also high switching energies. The operation junction temperature limits the highest acceptable power dissipation per MOSFET, which means the high switching energy limits the maximum switching frequency.

 

Proposed solutions

This chapter describes potential solutions, analyzes their effectiveness and looks at how these are put into practice.

 

Miller clamp circuit

A common way of removing the injected current from the device is to install an external Miller clamp circuit in the gate driver. The external clamp circuit’s effectiveness depends on the inductance between the clamp circuit and the MOSFET, and on the internal gate resistance.

The gate loop’s inductance is below 4nH, including the module’s pin, bond wires and DCB copper tracks.

In this case, the MOSFET’s internal gate resistor limits effectiveness — the higher the gate resistor value, the less effective the external Miller clamp circuit. The gate resistor in this example has several ohms, which prevents the charge’s removal.

 

Negative gate voltage bias

Another option is to increase the negative gate voltage bias until any parasitic turn-ON is undetectable. However, most suppliers limit the maximum negative gate voltage to a value of around -5 V, including all transients. Experiments show that a negative voltage spike ap-pears when the MOSFET is turning OFF. This spike imposes a limit on the static negative gate voltage as the sum of both may not exceed the maximum ratings. In that case, this solution is not an option.If the negative spike exceeds the given limits for device reliability, this will cause the gate oxide to degrade. This has a negative impact on long-term reliability because the threshold voltage may decrease to zero as the oxide deteriorates.

 

Figure 5: Low-side SiC MOSFET turn-OFF, Uds: light blue, Ids: dark blue, Ugs: yellow (Udc=600 V, Ids=140 A, Tj=150 C, Vg=-6/16 V)

 

ANPC with split output

Another proposed solution is to decouple the high- and low-side MOSFETs by splitting the circuit into two parts with a separation inductance in between.

The module’s pin stray inductance serves as the separation inductance. No additional external circuit components are necessary.

Two additional diodes have to be added in the power module to keep the circuit functional (figure 6).

 

Figure 6: ANPC with split output

The added inductance disables the given switch’s output capacitance, thereby preventing exposure to high dv/dt and Miller capacitance-induced charging injected into the gate. This first step can reduce the second current spike (figure 7), but not eliminate it all together.

 

ANPC with split-output and integrated gate capacitor

A further step can be taken to fully overcome the limitations imposed by the Miller effect: Install a capacitor in the module between the MOSFET’s gate and source (figure 8). The absence of a second current spike in figure 9 shows that this prevents parasitic turn-ON.

 

Figure 7: Low-side SiC MOSFET turn-ON with 50 nH separation inductance, Uds: light blue, Ids: dark blue, Ugs: yellow (Udc=600 V, Ids=140 A, Tj=150 C, Vg=0/16 V)

 

Figure 8: ANPC with split output and gate capacitor

 

The gate capacitor reduces dv/dt, which has the added benefit of reducing EMC.

 

Figure 9: Low-side SiC MOSFET turn-ON with 50 nH separation inductance and 10 nF gate capacitor, Uds: light blue, Ids: dark blue, Ugs: yellow (Udc=600 V, Ids=140 A, Tj=150 C, Vg=0/16 V

 

Conclusion

The above paragraphs describe and discuss various remedies to the root cause of the limitations of SiC MOSFETs operated in hard-switched, totem-pole applications. A SiC MOSFET has to operate reliably throughout its service life, so the main concerns to be taken into account here are the gate oxide and therefore the maximum positive and negative gate voltages. Exceeding the maximum device ratings in static or dynamic conditions may cause the gate structure to degrade and the threshold voltage to drift. This would eventually result in component failure and, as a consequence, device failure. A split output paired with an integrated capacitor between the gate and source as presented here can help overcome the limitations in switching performance and enable the device to be operated to its specifications.