austriamicrosystems Releases New Version Of High-Voltage CMOS Process Design Kit
austriamicrosystems announced a further improvement of what it describes as its industry benchmark design environment ("HIT-Kit") for its advanced 0.35µm High-Voltage CMOS process H35. It is said to be well suited for high voltage product design like power management products, display drivers, sensors and sensor interfaces and any kind of automotive applications.
The new HIT-Kit 3.72, based on Cadence version 5.1.41, includes updated periphery cell libraries up to 50V as well as the recently announced set of 20V devices optimized for power management products and display drivers in battery powered applications. In addition the HIT-Kit offers design utilities like a Safe Operating Area Check (SOAC) tool, automatic layout generators for high-voltage device and guard-ring generation and special layout verification utilities like leakage check. In combination with the highly accurate circuit simulation models these tools are said to enable high voltage chip designers to shorten their design time and increase their number of first time right designs.
"These new design tools and utilities are helping high voltage designers to do better simulation and gain more peace of mind towards completing their product design. We consider this another demonstration of us going the extra mile for our foundry customers", commented Thomas Riener, General Manager of austriamicrosystems’ Business Unit Full Service Foundry. "Our leading High-Voltage CMOS process technology in combination with an easy-to-use design environment and outstanding support enables foundry customers to achieve first time right designs at smallest possible die sizes."
The new Cadence HIT-Kit v3.72 contains a complete set of fully silicon-qualified standard cells, periphery cells and general purpose analog cells such as comparators, operational amplifiers, low power A/D and D/A converters. Custom analog devices, physical verification rule sets for Assura® DRC/LVS/EXT, as well as characterized circuit simulation models that are said to enable rapid design starts of complex high performance mixed-signal ICs.
All I/O structures within the design kit are silicon-validated and meet the military ESD and JEDEC latch-up standards with I/O pads designed to surpass up to 4kV HBM and 250mA latch-up immunity. The specialty High-Voltage CMOS process H35 with its floating libraries includes a total of more than 2400 core and periphery cells.
