Designing High Voltage GaN Switch ReliabilityApril 16, 2019 by Ronald Barr
This article highlights Transphorm Incorporated TPH3205WSQA device field reliability data for high voltage GaN power converters applications.
Transphorm has created an extensive body of reliability data across multiple generations of products that demonstrate the robustness of the platform; by extensive qualification testing and by having an in-depth understanding of failure modes and acceleration factors.
FIT Rates and Field Reliability
Transphorm is the first company to qualify high voltage GaN devices at 600V, 650V and 900V to the JEDEC standard; is the first to qualify 650V devices at 150°C and 175°C to the AEC-Q101 automotive standard; and is the first to publish intrinsic acceleration factors, extrinsic reliability data and field reliability data. This article will discuss the application of accelerated life test data to determine the intrinsic reliability of a commercially-available automotive-qualified GaN device from Transphorm. In addition, the world’s first Early Life Failure calculations and Field Reliability data for high voltage GaN power converters are presented. All tests are based on current JEDEC and AEC standards.
Unless otherwise noted, the device used in this paper is the TPH-3205WSQA produced by Transphorm Inc., located in Goleta, California. This device is a normally-OFF, two chip design with a D-mode GaN HEMT in series with an E-mode low-voltage Silicon FET. Vds(min)=650V, V(TR)DSSmax=800V, Rds(on)max=62mΩ, Tj max=150°C, TO-247 package. This device has been qualified to the AEC-Q101 automotive standard.
Figure 1: Cross-section diagram of Transphorm GaN device
High-Temperature Reverse Bias: OFF State Failure Mode and Acceleration Factors
High-temperature reverse bias (HTRB) OFF state testing has historically been a difficult test for GaN devices to pass. The reason for this is that under this condition there are very high electric fields between gate/field plates, drain, and substrates that can cause defects in the dielectric layers and eventually result in a TDDB catastrophic failure between the field plate and drain.
This failure mode dominates the OFF state failures regardless of whether the failure is caused by voltage or temperature acceleration. It shows up as wear-out failure (intrinsic) and also shows up as infant mortality failure (extrinsic), dielectric defect limited lifetime. The most likely explanation for early failures caused by dielectric defects sharing the same failure mode as the intrinsic failure is that defects in the dielectric and metal layers, in the wafer from the fabrication process accumulate charge and accelerate failure of the device in the region around that region due to changes in the electric field.
Voltage and temperature acceleration factors for this failure mode have been calculated. Though a detailed review of the methodology is beyond the scope of this paper, what follows is a summary of the test. Voltage acceleration was determined by testing to failure a sample of material at voltages between 1000V – 1200V. A linear time-dependent-dielectric-breakdown (TDDB) model was used, (other voltage models will give longer lifetimes, and unless there is either experimental or theoretical justification, other models should NOT be used). The Voltage Acceleration Factor (AFV) is defined in (1), where ΔV is the difference between the stress voltage and the usage voltage. The experimentally defined value for γ = .026 V-1.
Temperature acceleration factor (AFT) assumes an Arrhenius relationship and was generated by testing parts to failure at -20°C to +150°C at voltages ranging between 1050V and 1300V which results in an activation energy of Ea = -0.3eV. The temperature acceleration factor (AFT) is calculated with equation (2) as referenced. Note: k is the Boltzmann’s constant. The combined acceleration factor AF is simply the product of the voltage and temperature acceleration factors equation (3).
Figure 2: (clockwise from top) 1. Electric field diagram showing region of high damage. 2. Cross-section of failed device showing lateral burn mark. 3. Overhead SEM of failure showing short from gate to drain.
Intrinsic Failure Rate
Use-plot analysis gives a more complete picture of the intrinsic failure rate of the device by combining data from multiple wafers and utilizing the acceleration factors previously derived. The data is then normalized to typical use conditions, using the acceleration factors defined, to calculate the wear-out lifetime of the device. A standard convention is to define wear-out of the device when the probability of failure reaches 100 ppm. The use plot calculation of the data shows that, even at 150°C @480V, wear-out of the device begins after 108hours. It is important to understand that the Intrinsic Lifetime of the device is a very poor predictor of field reliability and instead one should utilize Early Life Failure Testing as defined in JESD74A.
Early Life Failure
Rates are used to calculate warranty risk, and to predict field failure rates. Early Life Failures include infant mortality as well as random failures during the useful life of the part (the time before the part wears out) as illustrated in the Bathtub Curve. Voltage and temperature accelerated tests on a large number of parts are used to generate an Early Life Failure Model.
Figure 3: The Bathtub Curve demonstrates a power device’s typical reliability via failure types over time.
Voltage acceleration testing can be used with GaN devices because they do not avalanche like a Silicon MOSFET. Instead leakage increases with voltage and eventually the device fails. In general, GaN can fail in one of two ways. Either laterally from the gate/field plate structure to the drain, or vertically through the insulating GaN buffer layer. This is a basic design consideration and could vary from manufacturer to manufacturer. The TPH3205WSQA device experiences vertical failure at voltages greater than 1300V, which enables Early Life Failure testing at voltages greater than the rated 650V, but well under the vertical failure voltage. It is important that all failed devices created by this test undergo analysis to ensure that the failure mode remains lateral gate to drain, and that new failure modes are not being introduced.
For this test, a total of 4,000 parts were tested. Most tests ran for 1,000 hours, though some tests were extended up to 3,000 hours. Voltages ranged from a low of 520V to a high of 900V. Temperatures ranged from a low of 25°C to a high of 175°C. A small number of parts from the 900V leg did experience failure, and these failures are included as part of the calculation. (Failures increase the chi-square statistic). Against a typical use condition of 400V/100°C, this represents over 30 billion device hours.
FIT Calculations were performed as per JESD74A. (Note: FIT = failure per billion device hours)
Early Life Failure (in FIT) = 109 x χ2 / 2 x A x N x tA
Where: χ2 = chi square statistic
A = acceleration factor
N = number of devices tested
tA = test time in hours
At maximum junction temperature (TJ max = 150°C), the following FIT values were generated:
While there are no absolute standards for FIT (lower is always better), values in the single digits for commercial products and values less than one for automotive products are generally considered a requirement.
In the end, actual field reliability statistics are the most relevant. Transphorm has shipped over 400k devices to customers in production with over 3 billion device hours in the field. In calculating field reliability, Transphorm makes a conservative calculation that assumes that only half the devices shipped are actually in the field and in use. Currently, Transphorm FIT = 2.2, or less than 20 ppm per year, which compares favorably with the FIT of other wide bandgap power semiconductors. Transphorm’s FIT rate continues to decrease as it was 3.1 at the end of last year.
The data presented shows that the TPH3205WSQA device exhibits reliability that is on par with other high voltage semiconductor devices, based upon an understanding of the physics of failure, acceleration factors, and the extrinsic reliability, and field reliability data.
 K. Smith et al., “Reliability Testing of AlGaN/GaN Power Switch Devices at Low and High Temperature” (2017 ROCS Workshop, May 2017)
 JESD85 Methods for Calculating Failure Rates in Units of FITs
 K. Smith et al., Microelectronics Reliability vol. 58 (2016) pp. 197-203
 JESD74A Early Life Failure Calculation Procedure for Semiconductor Components