Technical Article

A New Approach to Superjunction MOSFETs

November 23, 2017 by Tom Harrington

This article highlights the new approach of adding wafer-level configurability to high-voltage superjunction MOSFETs for power supplies.

D3 Semiconductor has entered the market with the intention of changing the DNA of superjunction MOSFETs. The company used a novel technique of adding configurability – at the wafer level – when developing its new +FET™ product line. This approach is already yielding design flexibility options never seen before.



A new approach of adding wafer-level configurability to high-voltage superjunction MOSFETs is now available to help solve power supply circuit issues. Offering a new level of configurability in slew rate, threshold voltage, on-resistance and ampacity of the MOSFET offers more control of system dynamics. It also gives the designer freedom to tune the MOSFET to the system – and to reduce time modifying printed circuit board layouts or prototyping magnetic options.


Typical Approaches

Noise and Efficiency Issues

Given the multitude of issues facing designers, the traditional approach is to consider the MOSFET a simple switch with given behaviors, performance and consequences. The remainder of the circuit is then designed to keep the switch operating comfortably in its safe operating area. Additionally, the external circuity is tuned to reduce noise generated by the MOSFET during its normal operation. From the outside looking in, it seems like rational approach, but the additional circuitry contributes complexity, cost and weight to the system.

The MOSFET can oftentimes be its own enemy in the circuit. Its normal operation generates high-frequency noise during its transition from off-on and on-off. During the on-off transition, this noise can be amplified by parasitic physical properties in the circuit components and board layout. If the amplified noise is coupled back to the gate/ gate drive circuitry, the amplified noise can then act to raise the gate voltage to a level high enough to turn-on the device and cause losses.

Adding an additional dimension to the challenge of noise mitigation is ensuring efficiency remains high. Product requirements dictate EMC compliance with the highest efficiency attainable. This leaves the designer pursuing every last 0.1% efficiency from a circuit.


Timing Constraints

Variations in threshold voltage and gate resistance determine system timing constraints that propagate into overall power supply efficiency ratings for the circuit utilizing the device. Tighter and more accurate control of threshold voltage and gate resistance distributions provides many advantages. There are several device parameters of this nature where the absolute value of the parameter is not as important as the width of the variation observed for the parameter. Tighter controls of these distributions would allow the designer the flexibility to make tradeoffs in the system design, improving a particular performance characteristic as needed for a particular application while mitigating electrical noise.

Various techniques have been employed over the years to tighten parametric distributions in a cost-effective manufacturing process, but none have been completely satisfactory.

One prior solution has been to concentrate on low-cost processing, test the resulting components, and sort the manufactured devices into various parametric distribution categories and to choose only those which are in an acceptable range. This is generally known as “binning.”

Another approach has been to modify the design of the components slightly to allow trimming with a laser or other post-fabrication techniques to shift large numbers of the parts into a desired parametric range. This has been successfully applied to mixed-signal circuitry in mass production. This method has not been successfully applied to vertical semiconductor devices.

The reason that trimming techniques are difficult to apply to vertical semiconductor devices is because the internal units making up the vertical device all have a common connection on the bottom side of the wafer. In order to implement trimming on devices with common terminals, novel techniques, such as those being implemented by D3 Semiconductor, are being employed.


New Approach

When developing its new +FET™ product line, D3 Semiconductor chose a nontraditional technology approach by applying integration to high-voltage superjunction power MOSFETs.

In a traditional transistor configuration, no elements are present to provide trimming capability, as shown in Figure 1.


Traditional transistor without trimming capability
Figure 1: Traditional transistor without trimming capability


By choosing to add control mechanisms in the circuit, choosing a transistor enabled with laser trimming provides an entirely new host of variables that can be defined by the designer. In particular, behaviors such as switching time, on-resistance, threshold voltage and ampacity can be defined, or configured, to the designer’s specifications within a range of choices.

This configurability is implemented by laser trimming the transistor device using multiple parallel device segments, as shown in Figure 2. The same method may be used to match the desired parameter from device-to-device and wafer-to-wafer. This translates into the capability of providing identically matched devices consistently over large-scale production runs.


Transistor with configurable gate resistor
Figure 2: Transistor with configurable gate resistor


The benefit to the designer is that one can have identically matched FETs in an H-bridge configuration (Figure 3) or parallel operation (Figure 4). Knowing the MOSFETs are identically matched allows system overhead to be reduced since the current flow in a given circuit will be predictable.


H-bridge circuit configuration
Figure 3: H-bridge circuit configuration.


In addition to trimming for dynamic behaviors, static parameters can be configured in a similar manner. Configuring threshold voltage, on-resistance and ampacity by targeting specific gate resistors and fusible links enables the designer to choose the optimum voltage for the targeted circuit, as shown in Figure 5. By utilizing a laser to create an open circuit in the gate region of the transistor during a standard manufacturing flow, the static parameters may be configured to a desired level.


Parallel circuit configuration
Figure 4: Parallel circuit configuration
Multiple device trimming to set static parameters
Figure 5: Multiple device trimming to set static parameters.


The benefit to the designer is that one can configure the threshold voltage at a level high enough to ignore circuit noise or low enough to capture lost efficiency in the gate drive circuit. When performing rapid prototyping and a specific on-resistance or ampacity is needed, trimming is implemented to remove transistor active area. The result is the ability to quickly deliver a wafer’s quantity of parts in a short period of time while meeting the designer’s requirements. When prototyping is complete and the project moves to mass production, a mask set is generated to target the specific threshold voltage, on-resistance and ampacity, so unit costs are optimized.

When developing the architecture of the D3 Semi +FET, considerations for laser trimming were made to keep the injection of laser heat from affecting overall transistor operation. Mixed-signal manufacturing techniques were applied without affecting cost of manufacturability.



Utilizing laser trimming in volume manufacturing has been performed for years. In the case of high-voltage superjunction power MOSFETs, employing this manufacturing technique is unique and groundbreaking. Not only does it open many new ways for the designer to pursue circuit optimization, this trimming option can be utilized for high volume production.


About the Authors

Tom Harrington is a co-founder of D3 Semiconductor.  He has more than 30 years of semiconductor industry engineering and management experience.  Most recently, Tom served as Managing Director of Technology Development for Maxim Integrated Products. Tom leverages his mixed signal experience from Maxim and Dallas Semiconductor to drive innovation into D3's power technology. He earned his Master's degree in Electrical Engineering and Bachelor's degree in Physics at Louisiana State University, Baton Rouge, LA 70803, United States.

Scott Carson is the Vice President in Global Sales and Marketing at D3 Semiconductor, a company specialized in power supplies and motor controls by fusing mixed signal precision with power semiconductors. He earned his degree in Bachelor of Science in Electrical Engineering at Texas Tech University, Lubbock, TX 79409, United States.


This article originally appeared in the Bodo’s Power Systems magazine.