STMicroelectronics Demonstrates New Ultra-Low-Power Technology for Energy-Efficient Applications

March 27, 2011 by Jeff Shepard

STMicroelectronics (ST) announced that it has successfully demonstrated a next-generation variation of its smart power technology. The new technology is expected to enable significant reductions in the power consumption of a wide range of electronic systems – from new medical equipment to battery chargers in hybrid electric vehicles.

The ever-increasing worldwide demand for electronic and electrical devices, together with the increasing global awareness that the use of fossil fuels to generate electrical power must be reduced as much and as quickly as possible, means that there is now a major focus on making end-use equipment significantly more power efficient. This focus has driven the development of this new technology from ST.

ST has already verified the feasibility of this new semiconductor technology by producing, in cooperation with a world-leading medical equipment supplier, a demonstrator chip for ultrasound scanners that can handle over one hundred channels, to address the next generation of scanners that will require thousands of channels. The best technology available today on the market does not allow this level of integration, with current chips typically handling only eight channels.

The development of the technology is one of the results of an advanced European R&D project. In Europe, the EU has stimulated much research and development work in this field through the ENIAC (European Nanoelectronics Initiative Advisory Council) initiative. Within the ENIAC framework, ST and 17 other European partners have formed the SmartPM (Smart Power Management in Home and Health) consortium to answer this growing need for energy efficiency. The SmartPM consortium includes companies and academic institutions from nine countries: Belgium, France, Germany, Ireland, Italy, the Netherlands, Norway, Spain and Sweden. The SmartPM partners are working together to develop innovative semiconductor technologies, circuit designs and system architectures.

"Semiconductor technologies that can drastically reduce electrical energy consumption in consumer and industrial appliances have existed in the labs for many years and their potential contribution to the reduction of worldwide power consumption is significant," said Claudio Diazzi, Group Vice-President, Technology R&D, STMicroelectronics. "However, the cost of these technologies has previously been too high to make them commercially viable. We believe that this new smart power technology will make a significant difference."

The new technology is a next-generation variation of ST’s world-leading BCD (Bipolar-CMOS-DMOS) smart power semiconductor technology that combines SOI (Silicon-on-Insulator) substrate technology with 0.16µ lithography. This will enable chip designers to combine high-density logic circuitry (1.8 and 3.3V CMOS) with full dielectric isolation and a component portfolio including power MOSFET transistors that can operate up to 300V, low noise devices, and high-value resistors, leading to ASICs that cannot be implemented using conventional bulk-silicon substrates.