Imec Demonstrates Backside Power Delivery Network for Enhanced System Performance

The primary goal of a power delivery network (PDN) in a VLSI chip is to provide sufficient power lines across the chip to power the active devices on the die. This network generally starts at a power supply. A series of metal layers and vias connect the transistors to the main power supply. 

Along the path, the power is affected by parasitic capacitances, wire resistance, and inductances. Therefore, the voltage supplied to the device may not be a perfect replica of the main power supply. In addition to this, for powering different subcircuits, voltage regulators are utilized along the path. Thus, delivering power to devices across the chip is complicated and expensive. It also takes up a large area as it employs voltage regulators, references, capacitors, etc. along the path.

Signal network and power delivery networks are generally fabricated through back-end-of-line (BEOL) processing on the front side of the wafer. In this commonly used approach, the layout complexity increases, and the noise due to the signal lines in the power supply lines also increases. Imec intends to move the power delivery network to the backside of the wafer. The proposed approach promises to enhance system performance, increase the chip area utilization and reduce BEOL complexity.

Arm engineers, in collaboration with Imec, earlier showed that using the traditional approach of making power delivery networks, too much power was wasted in the interconnect networks resistance. On the other hand, the final variation where the backside power delivery network was connected to the buried power rail presented only a 1% drop in voltage without affecting the performance [2].

However, the complexity involved in manufacturing the backside power delivery network is considerable. For realizing a backside power delivery network, a dedicated wafer thinning process is necessary with the ability to process nano-through-silicon-vias (n-TSVs) that connect the backside and the front side of the device wafer. These processes are being developed and optimized in the frame of Imec's 3D integration program.

Realization of the backside power delivery network using nano-TSVs and BPR technology. Image Courtesy of Imec.

In five papers presented at the 2021 VLSI Symposium, Imec reports progress in developing and manufacturing the backside power delivery network. The authors also demonstrate the new design options to optimize the backside power delivery for scaled systems.

In the 2021 VLSI paper by A. Veloso (and others)., the authors evaluate the impact of backside wafer thinning and n-TSV fabrication on the properties of scaled Si-channel FinFET devices with a gate length of >=20nm built on the wafers front side [3]. The team observed no negative impact on the performance of FinFETs, except for a slight degradation of the PMOS drive current. Findings suggest higher electron mobility and drivability of up to 15% for nMOS devices. The following figure demonstrates the improvement in electron mobility after backside processing.

nMOS devices exhibit improved electron mobility after backside processing. Image Courtesy of Imec

 

New Design Options to Optimize Backside Power Delivery

There are several aspects to the analysis and design of a power delivery network, such as IR drop, electromigration, voltage noise, and increased power density. The VLSI paper by Geert Van der Plas and Eric Beyne highlights new methodologies to realize effective power delivery networks for scaled systems [4]. Geert Van der Plas, Program Manager 3D system integration program at Imec, says, "Removing the power delivery as well as the power conversion from the logic die's frontside to its backside can boost the system performance by specific designs." He explains it with an example of a metal-insulator-metal capacitor (MIMCAP). MIMCAP decouples the critical cells from the main power supply to protect those cells from disturbance like transistors switching in power lines. The Imec team showed that integrating MIMCAP in the wafer's backside can reduce the supply bounce by a factor of 15.

The paper by H. Lin et al. demonstrates how such an integrated MIMCAP can also be part of a charge pump that serves as a down-conversion integrated voltage regulator with 91.5% efficiency [5]. Another paper by the same author discusses an implementation of a power converter for backside power delivery [6]. Using a laterally diffused power MOS along with an off-chip package integrated transformer, they achieved a lower voltage of ~12V to ~1V (at transistor level) inside the package and avoided large currents through the solder balls.

 

I/O Implementation Challenge 

Backside power delivery network not only comes with manufacturing challenges but also affects the I/O implementation on the chip. The paper by W.-C Chen evaluates the impact of a complete backside power network on I/O performance and layout options to reduce the extra capacity [7].

 

About Imec

Imec is an R&D research center for nanoelectronics and digital technologies. They combine very talented people and world-class infrastructure to enable a prosperous and sustainable future for all. The R&D group brings together 4,000 brilliant minds from almost 100 nationalities. Imec focuses on creating groundbreaking innovation in application domains such as healthcare, smart cities, mobility, logistics and manufacturing, energy, and education.

 

References

• ‘Imec demonstrates critical building blocks for a backside power delivery network’ Imec research update
• ‘Arm shows backside power delivery as path to further Moore’s Law’, IEEE Spectrum
• ‘Enabling logic with backside connectivity via n-TSVs and its potential as a scaling booster’, A. Veloso et al., VLSI 2021
• ‘Design and technology solutions for 3D integrated high performance systems’, Geert Van der Plas and Eric Beyne, VLSI 2021
• ‘91.5%-efficiency fully integrated voltage regulator with 86fF/μm2-high-density 2.5D MIM capacitor’, H. Lin et al., VLSI 2021
• ‘Backside power delivery with a direct 14:1/19:1 high-ratio point-of-load power converter for servers and datacenters’, H. Lin et al., VLSI 2021
• ‘External I/O interfaces in sub-5nm GAA NS technology and STCO scaling options’, W.-C. Chen et al, VLSI 2021