$13.5M for Large-Diameter SiC Substrates for SiC and GaN Devices
The US Department of Defense's Air Force Research Laboratory, Sensors Directorate, Devices for Sensing Branch (AFRL/RYDD) has issued a Request For Information (RFI) titled 'Development of Large Diameter Silicon Carbide Substrate and Epitaxial Processes' (solicitation number RFI-AFRL-RQKS-2016-0002) to obtain information about potential sources with demonstrated expertise and experience to meet the Air Force's technical development requirements in large-diameter silicon carbide substrates and epitaxial processes.
The Air Force need for sensors extends from dc to the radio-frequency spectra focusing on microwave through sub-millimeter wave (300MHz–300GHz). Exploitation of homo/hetero-epitaxial devices fabricated on SiC holds promise for revolutionary improvements in the cost, size, weight and performance of a broad range of military RF and power management and distribution components, it adds.
GaN high-electron-mobility transistors (HEMTs) are rapidly becoming the technology of choice for high-power RF applications, but GaN RF devices are dependent on the use of high-quality, semi-insulating silicon carbide (SiC) substrates, notes the RFI. The combination of high voltage and current handling as well as switching frequency capabilities make SiC-based power devices a viable alternative to silicon technology, it adds.
The fabrication of SiC power devices requires homo-epitaxial growth of precisely doped SiC layers ranging in thickness from a few microns to >100μm, depending on the voltage requirements. Critical to the realization is the availability of affordable, high-quality, large-diameter SiC substrates and epitaxy from a pure-play supplier. AFRL says that it is therefore interested in advancing the technological state-of-the-art with respect to SiC growth and fabrication.
Key technical requirements related to the RFI include: To demonstrate the axial gradient transport (AGT) crystal growth process to enhance quality, producibility and furnace throughput for conducting (N-doped) and semi-insulating (V-doped) SiC boules up to 200mm diameter; To demonstrate vanadium as a background dopant to achieve uniform boule radial and lateral resistivity of >1012ohm-cm for 4H- and 6H-SiC boules up to 200mm diameter; To demonstrate the fabrication and polishing of conducting and semi-insulating SiC substrates up to 200mm diameter that exceed existing state-of-the-art practices;
To demonstrate substrate and epi defect reductions that are an order of magnitude below existing industry availability, enabling cost reductions in excess of 50% for both substrates and epiwafers; and To demonstrate SiC epi growth rates exceeding 60µm/hr of high-quality epitaxial layers with uniform thickness and doping densities on wafers up to 200mm diameter that are supportive of a broad range of device structures, including but not limited to Schottky diodes, metal-oxide-semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), and bipolar junction transistors (BJTs).
