Unlocking the Full Potential of SiC MOSFETs

July 13, 2022 by Darshil Patel

Commercial SiC MOSFETs are derated due to issues with gate oxide reliability. Optimizing the gate oxide reliability can reduce the specific on-resistance of the SiC MOSFETs and costs.

The Silicon Carbide (SiC) industry is growing rapidly as the SiC power switches deliver efficient, high power, fast switching, and compact power solutions. SiC MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) offer a low on-resistance (resistance when the device is in conduction mode), making them suitable for power electronic circuits, where reducing losses during current conduction without high switching losses is essential. Also, SiC devices are beneficial for protection circuits that carry currents continuously. Therefore, lower losses are critical for keeping efficiency high and thermal management simpler.


Image used courtesy of Andrei Kuzmik/Adobe Stock


SiC MOSFET manufacturers consistently reduce the specific on-resistance of their devices by 30% to 40% with each new device generation. This trend is beneficial as a decrease in on-resistance leads to an increase in current density. As a result, the area of dies can be reduced while maintaining a given current rating, which in turn increases the number of dies per wafer and results in a greater yield.

On the other hand, silicon MOSFETs have reached their technology limit, and no further reduction of the specific on-resistance is possible. SiC offers significant room for improvement as the on-resistance of the 1200 V devices is 14 times greater than the theoretically possible value.


Major SiC Resistances

SiC MOSFET consists of many major fixed and dependent resistances contributing to the total MOSFET resistance. Among them, the drift resistance or n-type epilayer resistance scales with the rated voltage and is the largest resistance among all. The other fixed resistances include substrate resistance, channel resistance, and junction resistance, from where the current is forced to conduct in a narrow channel between the source and the drain.

Apart from this, there are resistances associated with the termination regions around the edges of the current-carrying area. These inactive non-current carrying areas are required to maximize the breakdown voltage and implement gate pad contacts.


Gate Oxide Reliability Issues of SiC MOSFETs

SiC MOSFETs are designed with smaller gate oxide thickness and higher electric fields. As a result, SiC MOSFETs are unreliable due to high leakage currents during abnormal operating conditions.

Commercial 650 V rated SiC MOSFETs break down at 1250 V, which is in contrast with the trend of scaling down on resistance. To achieve low on-resistance, the breakdown voltage must be just a bit higher than the rated voltage.

The reason for this is related to gate oxide reliability. Gate oxide reliability is proportional to the electric fields across it. Moreover, SiC MOSFETs are known to withstand high electric fields at the surface, and as Gauss' law dictates, the electric fields at the gate oxide would be significantly greater than at the surface. Therefore, if a 650 V rated MOSFET breaks down at 700 V, then high electric fields at the gate oxide will cause the device to fail.

However, derating the SiC MOSFETs to 50% of their potential voltage rating prevents SiC devices from operating at their full potential. Therefore, solving the issues of gate oxide reliability is a priority for chip manufacturers as it will help further reduce the on-resistance and the derating.


Feature image used courtesy of Andrei Kuzmik/Adobe Stock