Technical Article

Output Ceramic Capacitor Roles in POL Applications

October 03, 2016 by Chris Burket

This article provides a discussion on the basic understanding of the importance of multi-layer ceramic capacitors and relevant key parameters.

Today’s power supply design engineers have many design aspects and priorities that need to be considered. Design priorities tend to be in the following order: topology, controller, FET switch(es), drivers (if stand-alone), magnetics, power passives, and finally, which multilayer ceramic capacitors (MLCCs) to use and how many.

As long as MLCCs are available that meet design needs, at least on the datasheet, MLCCs remain a low priority. Granted, all of the devices in the power converter are important, however, MLCCs play multiple roles within power supply designs with numerous parameters being involved. All of these roles end up being important to the converter’s performance, and especially in high-density Point of Load (POL) power applications with complex output capacitor solutions.         


What are Multilayer Ceramic Capacitors (MLCCs)?

MLCCs are known for their small size, high capacitance density, and low equivalent series resistance (ESR) and inductance (ESL) values. However, typical parameters provided by MLCC suppliers are case size; capacitance and tolerance; temperature characteristics; and voltage rating. The power supply designer needs to know effective capacitance (actual in-circuit capacitance), ESR and ESL values, ripple current (RC) handling and cost. Some power designs specifically target a minimum capacitance (C value), and maximum ESR and ESL values for a given output capacitor solution. This is especially true in high transient applications.


Equivalent Circuit Model of an MLCC
Figure 1: Equivalent Circuit Model of an MLCC


Figure 1 shows the MLCC equivalent circuit model where the hysteresis resistance (Rh) is a frequency-dependent value (which relates to the dielectric material used and its respective polarization delay) and is reflected as a changing ESR value in the ESR- /Z/ versus frequency curve shown in Figure 2:


ESR, /Z/ vs. Frequency
Figure 2: ESR, /Z/ vs. Frequency


The well-documented capacitance change due to temperature is dependent on the dielectric material and yields a known capacitance change over a defined temperature range. However, another contributor that affects effective capacitance is the applied DC voltage, typically called the “DC Bias effect”. As the applied DC voltage increases, the dielectric constant (K) and capacitance both decrease as a temporary phenomenon. Additionally, as an applied AC voltage decreases, the effective C value also decreases. This AC related decrease is important in low voltage applications where ripple voltage control is critical such as in Vcore designs for CPUs. See Figure 3.   


DC/AC Voltage Effects on MLCCs
Figure 3: DC/AC Voltage Effects on MLCCs


ESR values of MLCCs are dependent on many parameters. Key factors include:

  • Case size
  • The number of layers
  • Inner electrode material, thickness, coplanarity, density, and length/width aspect ratio
  • Applied DC voltage (like with capacitance)
  • Frequency

ESL values for MLCCs are dominated by the case size and their length/width aspect ratio of the inner electrodes. ESL is typically given per case size. Additionally, the number of external terminations and their configuration also impact ESL.

Ripple current rating, though no industry standard exists, relates to a specific self-temperature rise due to I2 x ESR losses, which create heat. Therefore, the ripple current value is dependent on frequency and DC voltage and its curve is the inverse of the ESR curve. A typical MLCC RC versus frequency curve is shown in Figure 4a:


Ripple Current vs. Frequency
Figure 4a: Ripple Current vs. Frequency
Temp Rise vs. Ripple Current
Figure 4b: Temp Rise vs. Ripple Current


which is for a specified self-temperature rise (ΔT) maximum. The maximum allowable ΔT may vary supplier to supplier. Figure 4a lists the ΔT as +20oC which is very conservative for capacitors rated up to +85oC or +125oC. In lower ambient temperatures, the MLCCs can be subjected to higher ripple current and still meet the rated temperature (Toperating = Tambient + ΔT). In this example, the MLCC ripple current capability ranges from 0.25A (1000 Hz) to 2.25A (1 MHz). Having accurate capacitor frequency-dependent information is a must in order to design in the proper output capacitor solution. Also, MLCC suppliers may provide RC vs. temperature rise but must specify at which frequency the curve is being generated for. An example of this is shown in Figure 4b.       

With this understanding, the following sections will address a few of the many key roles that the output MLCCs perform in a typical POL Buck power supply (used for simplicity). Highlighted roles are:

  1. low- pass filter
  2. ripple voltage suppression
  3. ripple current handling
  4. energy storage,
  5. transient response
  6. load dumping
  7. transient voltage spike suppression.


Low-Pass Output Filter (Sometimes called RF Output Filter)

In the Buck converter, the value of the output inductor (L), along with the equivalent output capacitor-C value, form a low-pass filter (LPF). The frequency response of this filter has a corner frequency, fc, at:


which is used to remove the converter’s fundamental switching frequency (Fsw), its subsequent harmonics and also to decouple any AC content and switching transients from the desired DC current flowing to the output load. This also includes helping to smooth out the triangular current waveform of the output inductor. For proper performance, the corner frequency of the low pass filter needs to be well below the Fsw. Due to this, the C value of the output MLCC(s), its tolerance and stability over various conditions, including DC Bias effects, all need to be considered.                        


Ripple Voltage Suppression (Smoothing)

Ripple voltage, assuming a steady-state load, is the difference in output voltage across the load and output capacitors during the ON time and OFF time of the Buck converter. During the ON time, where AC + DC current is being supplied through the inductor, the AC current flows into the output capacitor for recharging (to some maximum voltage level) and the DC current flows to the load.

During the OFF cycle, the energy starts to drain from the output inductor (through the collapsing of the magnetic field) since no input current is being sourced and the output capacitors become the secondary (if in continuous conduction mode, CCM) or sole energy source (if in discontinuous conduction mode, DCM). With a stored energy of E = 1/2CV2, the output capacitors supply the current to the load, and as they do, the voltage level starts to drop (aka voltage droop or Vdroop) as the energy is being drained from the capacitors for the remainder of the OFF cycle. The droop amount is dependent on the load current, the output inductor value, the OFF time and the total C value (higher = better suppression) and ESR value (lower being better since this reduces the internal voltage drop V = I x R) and the ESL (lower = faster response) of the output capacitors. The designer needs to know each of these per MLCC in order to determine the system C, ESL and ESR values. One of many equations used to calculate the minimum C value is:


where Iripple is the allowable ripple current and Vripple is the allowable ripple voltage. Higher Cout value means higher costs.


Ripple Current Handling

Ripple current is the difference of current flowing into, and out of, the output capacitors during the ON cycle (into the capacitor) and the OFF cycle (out of the capacitor). The internal varying capacitor AC current causes self-temperature rise due to I2 x ESR power losses. To accommodate higher ripple current, the designer would need to use either lower ESR capacitors (i.e., higher capacitance or specialty MLCCs) or use more pieces of the existing capacitor, which also reduces the amount of current subjected to anyone capacitor. Depending on how much temperature increase, the ambient temperature, and the time duration, potential MLCC failures could occur if sufficient ripple current handling capability isn’t designed in.           

For many Buck converter applications, the controlling factor for output capacitor selection is ripple current handling capability. Therefore, the key parameters of the MLCCs are ESR (maximum) values and ripple current (minimum) ratings.


Energy Storage

As mentioned, the energy stored in a capacitor is E = 1/2CV2. The larger the C value, the more energy that is stored. But the designer needs to compare energy storage needs versus size, weight, quantity, board space, frequency response, product lifespan (aging effects) and cost trade-offs. Ripple voltage, ripple current, voltage droop, system ESR values, and ripple current handling per capacitor all will affect the C value needed and therefore, impact the energy storage of the output capacitors. Energy storage, in terms of the voltage and the capacitance, determines how long the “hold up” time will be during the OFF cycle or in the event of loss of power. For this key function, the C value, tolerance, temperature, and DC Bias effects are the key MLCC parameters.  


Transient Response

In the complex real world of power electronics, the load can be varying and have load step-ups (i.e. the load increases) that equate to hundreds of amps per microsecond (di/dt) or higher (ex: server CPUs). For these cases, the converter (or voltage regulator, VR) cannot respond as it needs to wait for some feedback signal notifying it that there is a load change. Likewise, the current through the output inductor cannot change instantaneously and thus, cannot react fast enough since it needs to build up its magnetic field prior to being able to supply the additional needed current demanded by the load. The only energy sources that can react to these extreme requirements are the output capacitors in the Power Distribution Network (PDN).            

Due to their low ESR and ESL values, MLCCs are one of a few capacitor technologies that can provide the performance needed during high di/dt events. However, standard configuration MLCCs still cannot provide the needed performance in the most stringent applications. The internal ESL of the capacitor must first be “saturated”, that is, build up the small magnetic field (H) which inhibits current flow, prior to being able to start responding to the load change. Therefore, specialty capacitors like reverse geometry capacitors, where the terminations are placed on the MLCC sides or MLCCs with special internal electrode configurations and multi-terminations, reduce both ESR and ESL dramatically.

Until the MLCCs can react to the load change, the system voltage level will begin to drop and may fall below a critical minimum level (e.g. Vcc tolerances of CPUs) if the output capacitors cannot source the load current for enough time until the other energy sources begin to react as well. The low ESR/ESL MLCCs are the first line of defense to minimize the voltage droop but may not have enough bulk energy storage to do it completely on their own.

During the transient event, the MLCC response is first limited by its ESL, which initially prohibits the current flow out of the (nearest-to-the-load) capacitors. The next phase of response is dominated by both the ESL and ESR and involves the next bank of capacitors. The third stage is ESR and C value-dependent involving the bulk storage capacitors and finally, recovery occurs by other storage devices and the VR beginning to source more current. The basic equations for voltage droop contributors within the output capacitors are:                       


where: (Eq. 3 is high-frequency transients);
with a simulated response for a multiple capacitor technology solutions in Figure 5a, for the PDN network shown in Figure 5b:  


Voltage Drop During Transient
Figure 5a: Voltage Drop During Transient
High di/dt Capacitor Scheme of PDN
Figure 5b: High di/dt Capacitor Scheme of PDN


In transient response scenarios, ESL is critical and MLCC suppliers continue to strive for lower solutions. Designers target a maximum value for each output capacitor technology and also reduce PCB layout stray inductances. Another key parameter is ESR and usually, the focus is to minimize this value to meet a maximum target. Lastly, the capacitance value and its bulk energy storage are needed to supply energy until the converter’s control loop can respond and the converter starts to supply energy to the load and recharging the capacitors in the PDN. Here, the designer requires a system minimum value typically for each capacitor technology.


Load Dumping

Another extreme scenario is load (energy) dumping which also occurs when there is an abrupt decrease in the current demand (load step-down) … like when the CPU goes into idle mode. Here, the magnetics are saturated with stored energy (E = 1/2LI2) during high load current demand. When the load path to the source is no longer there, the only remaining outlet for the current to take is through the output capacitors. Due to this, the design engineer needs to consider trade-offs in the inductance value. Too small of a value allows too much ripple and too high of a value potentially stores too much energy, requiring additional output capacitors to handle the load dump.                                                       

The increased current going to the capacitors creates higher power losses (Ploss = I2 x ESR) and may cause thermal issues much like for high ripple current mentioned above. Also, with the increased current being dumped into the capacitors, there may now be an excessive voltage spike. Therefore, the designer needs to balance the inductance value and its stored energy with the output capacitance and its energy storage capability and ensure that there is enough capacitance, low enough ESR to handle the energy being dumped by the inductor.  


Transient Voltage Spike Suppression

As mentioned above, transient events can be a load step-up or a load step-down. Since the slew rate of the output inductor current increases faster than it decreases (when Vin > Vout), the transient during step-down is more critical. During the step-down change, and like for load dumping, the inductor current no longer flows 100% to the load since its demands have dropped substantially. Therefore, a large percentage of the current now must flow through the output capacitors, since:


where IL is the inductor current, IO is the output load current and IC is the current through the capacitor(s). These are shown in Figure 6:


Load, Inductor, Capacitor Currents During Load Step-down
Figure 6 – Load, Inductor, Capacitor Currents During Load Step-down


Also, just before the step-down transient event, the voltage of the output capacitors would be at or near their maximum value if at a constant high load. Therefore, with the pre-existing capacitor voltage and the voltage drop due to a large current flowing through the capacitor across both the internal ESR and ESL, this introduces a voltage spike across the capacitor and load during the transient. The output voltage waveform during the step-down transient can be calculated as:        


which are the combined Vdroop equations previously given but for current now flowing into the output capacitors and causing a voltage increase? Looking at what occurs at a micro-level, the slower reacting inductor current IL cannot follow the fast-changing load current IO demand, therefore IC goes through the output capacitor’s ESRC and its ESLC. Both the pre-existing capacitor charge and the ESRC and ESLC voltage drop from the output voltage spike that is created during the transient period. This voltage spike then lasts until the energy is drained from the output inductor IL and the voltage regulator has now adjusted itself to provide reduced current.       

Smart systems, such as CPUs and VRs, incorporate functions like Adaptive Voltage Positioning (AVP) which help reduce the effects of a transient voltage spike in sensitive applications, but much of the burden still falls upon the output capacitors and therefore, their ESR and ESL values are critical in minimizing the peak value of the transient voltage spike. The lower these values, the lower the voltage spike peak.


Importance of Multi-layer Ceramic Capacitors

All of the above roles are meant to provide the designer with a basic understanding of the importance of multi-layer ceramic capacitors and relevant key parameters. Each of the functions and respective capacitor solutions needs to be calculated, modeled, simulated and tested prior to design completion. Additionally, it is important to know that all of the capacitor parameters can vary significantly from one supplier to another supplier, even if similar on paper, so it is also important to compare actual samples with supplier data curves and those from other suppliers.                                                                         

As experienced power engineers know, there are many other considerations for which MLCCs play a major role which cannot be addressed here due to limited space. Other key roles include:

  1. control loop compensation and stability
  2. Phase and Zero-setting
  3. EMI suppression and load bypassing,
  4. load line impedance matching
  5. load noise filtering
  6. efficiency improvement.


About the Author

Chris T. Burket joined TDK Corporation of America in 1995 and has held several Sales, Marketing and Engineering positions. He has been involved in product design, technical sales and marketing, and has been awarded over 20 worldwide. patents. Chris' current position is as a Senior Applications Engineer supporting Wireless Power Transfer shields, coil assemblies and modules, as well as numerous other related passive components. Chris currently resides in TDK's Orange County, CA office but his supports North and South America and New Zealand. 



  • Jeff Boylan – TDK-Lambda Americas, EVP of AC-DC and DC-DC Power Supply Product Group
  • Ed Stanford – CTO of Power Delivery Consultants, LLC,
  • Gus Mehas – Integrated Device Technology, Director of Technical Staff, power guru
  • Dissertation Paper – “High-Frequency and High-Performance VRM Design for the Next Generations of Processors” – Kaiwei Yao, Virginia Polytechnic Institute and State University, 2004


This article originally appeared in the Bodo’s Power Systems magazine.