Low Loss and Low Forward Voltage Drop SIPOS Passivated Fast Recovery DiodeApril 08, 2020 by Subhas Bose
A family of 1700V 25A to 300A FRDs shows low switching losses and low forward voltage drop with a positive temperature coefficient.
This article introduces a new family of 1700V 25A to 300A Fast Recovery Diodes (FRDs). The experimental findings are consistent with numerical modeling results and demonstrate that using Variation in Lateral Doping (VLD) employing SIPOS, SIN and polyimide passivation, it is possible to achieve a stable 1700V diode. The devices show low switching losses and low forward voltage drop with a positive temperature coefficient.
To increase the avalanche breakdown voltage, to improve the switching power losses for example in windmills, induction heating, motor drive or inverter applications, there have been many efforts concerning the development of optimized diodes called first, second, third and fourth generation FRDs. The main development of these new generation diodes using bulk wafer, Thin wafer technology, n+ back surface contact, laser annealing, and multiple proton implantations were all employed for diode fabrication [1-5].
In this article, a 1700V soft recovery diode with different current ratings is introduced. The fast and soft recovery diodes with tail current were developed using a combination of deep diffused phosphorous wafers from the backside of a wafer and controlled axial lifetime killers. The proposed diodes give stable performance throughout their operating temperature range and maintain positive forward voltage drop with respect to temperature.
These diodes are designed for medium to high-frequency applications where low and high switching performance is required. The switching losses at RT and hot compared with respect to competitor devices. Furthermore, to our knowledge, we have found out that an economical approach to fabricate power diodes is using commercially available 6-inch 600V to 1700V deep diffused phosphorus wafers instead of using multiple proton implantation to get N buffer region. If one needs thin wafers for example like 600V to 1200V, thin wafer technology can be implemented using final Phosphorus implantation and laser annealing to activate Phosphorus prior to backside metallization.
Figure 1 shows the simplified cross-section of the proposed VLD design. The structure is fully compatible with a 1700V to 4500V IGBT process technology. To provide consistency with the process conditions, the structure has been derived directly from DIOS and subsequently analyzed using TCAD simulation software. Great care has been taken to ensure a close fit between measured spreading resistance profile and that of the simulated profile. Since SIPOS is a semi resistive layer and difficult to implement in a breakdown voltage simulation tool, therefore zero charge is assumed. Deep P- region incorporated to reduce leakage current from axial lifetime killers such as Helium or Proton and to make the device robust during hard switching conditions.
Figure1: Cross-section of a Planar junction VLD termination for 1700V device.
Figure 2: Conventional spreading resistance profile of a 1700V soft recovery diode.
In an effort to obtain soft recovery diodes at all conditions StarPower has developed a 1700V diode by using phosphorus deep diffused wafers and axial lifetime killers as shown in Figure 2. The controlled axial lifetime killer inside the main boron is used to control the injection efficiency of holes from the P region. P- region used to reduce leakage current with respect to Anode boron junction depth and Metal thickness tolerances.
The same P region also reduces curvature effect so that during hard switching test conditions, current crowding does not occur. The soft N as shown provides extra charge for the soft recovery. The low injection efficiency of holes makes the device Vf positive temperature coefficient with an increase in temperature which is good for parallel operation of diodes in modules where several IGBTs and Diodes are connected in parallel, and during high temperature switching losses are minimized. Diode softness Trr is controlled using additional uniform lifetime killing by electron irradiation.
The requirements of FRDs are (a) Area efficient termination (b) Reliability (c) switching performance.
Area Efficient Termination
The Anode active area can be increased when the area of a termination is reduced for a given die size. As the active area increases the current capability of a device increases, Vf decreases and surge current increases. Premature edge breakdown is a very common effect in power devices. The breakdown takes place at the surface of the P/N- base junction due to curvature and a lower surface critical electric field. To avoid edge breakdown, the most commonly used techniques are floating ring termination [7-11].
This technique is based on P floating rings placed at the edge of the device to release the depletion width or share potential drop between the rings. However, this structure is passivation charge sensitive. To reduce charge sensitive spacing between rings should be reduced and more rings should be added. To reduce surface charge effect, the field plate technique can also be used in combination with the floating ring termination [12-15]. However, in both cases P rings do not completely deplete and do not share potential with N- and not area efficient. Therefore, VLD technique is used.
The VLD technique is based on implantation through small openings in the oxide using photoresist mask and subsequent drive in, leading to a controlled doping profile [156-17]. The slope in the lightly doped region and concentration of the doping profile as shown in the proposed structure Figure 1. VLD structures are sensitive to the doping concentration boundary between the main junction and the junction termination.
Therefore, ISE software is used to optimise the boron dose with Si thickness of 290um with effective N- thickness of 155um. 1700V VLD designed such that with 10% variation in doping concentration, breakdown voltage varies between 1900V to 2000V. Modern implanter dose variation is also within the range of 2% therefore it is possible to get minimum 1900V. Total width of a VLD design is 300u with redundant area between edge of VLD to channel stopper is 100um.
When the device is in avalanche breakdown voltage VLD completely depletes to the surface. If proper choice of passivation is not made, reduced breakdown voltage or unstable blocking characteristics or increase in leakage current occurs. Therefore, SIPOS passivation is made to deposit directly on the silicon surface. This is because SIPOS has got limited conductivity, any undesired charge such as ionic contamination, interface charge or trapped charge which may disturb the electric field distribution is compensated by mobile carriers within the SIPOS. LPCVD machine is used to deposit 0.2um of SIPOS with SIN passivation.
Conductivity of SIPOS is carefully adjusted by oxygen during deposition. Furthermore, we have observed that reverse leakage current increased at higher temperature because of thermally activated conductivity of SIPOS. However, this leakage current at 150°C is negligible or below our chip/module limit. Prior to the official release for mass production 75A and 200A went through full qualification testing. The most important reliability tests for the electrical stability of the chip are high Temperature Reverse Bias (HTRB) and humidity test. The HTRB test checks the ability of the samples to withstand a reverse bias while being subjected to the maximum ambient temperature that the parts are rated to withstand.
The condition used for the HTRB test is 80% of rated voltage at 150°C. The breakdown voltage and leakage current were measured before starting the test. 1700V chips (78+78 =156 chips) were assembled into the C6 package. The test was conducted for up to 1000Hr and readings were taken once every 8H. Pre and post measurement results show 10uA and there is no increase in leakage current. Humidity test checks the ability of the package and chip to resist moisture penetration. The sample is loaded into an environmental chamber. The relative humidity is then increased to 85% and the temperature is elevated to 85°C. The device characteristics are measured before starting the test. The devices are re measured after cooling down for 3hr. Pre and post measurement results show there is no increase in leakage current.
Figure 3: VLD breakdown voltage with respect to Boron dose.
Figure 4(a): Forward voltage drop at 25°C and 150°C Figure 4(b) Switching performance at 25 and 150°C
The maximum leakage current at room temperature is 10uA and at 150°C 1mA.
(c) Switching performance
In order to verify the performance of the StarPower FRD diode in comparison to two competitor FRDs at 25 and 150°C were carried out using an inductive load circuit. The forward voltage drop of all diodes are within +/. 0.15V. After axial life time killer and electron irradiation devices were tailored to Vf 1.8V using vacuum annealing furnace. Figure 4(a) On state characteristics show that at rated current and above Vf increase with increase in temperature. This makes a better choice for parallel operation. Typical switching results are as shown in Figure 4(b) at RT and 150°C for 75A Vr at 900V and di/dt 1500A/ us.
The switching results show that there is no over shoot voltage. Therefore, devices can be stressed to higher blocking voltage. Table-1 shows comparison results of competitor devices for identical chip sizes. The reverse recovery waveforms and Table-1 results show that the diode does not ring and therefore produce low EMI, results in removal of parallel RC snubbers across the diode. Comparing RT to 150°C maximum reverse recovery current (Irm) value increase is 25% therefore IGBTs will be less stressed across the temperature range in real application.
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Table-1: Switching condition at 75A,Vr-900V Rg 10ohm and di/dt-1500A/us
Simulation analysis and practical results show that by using VLD structure it is possible to obtain breakdown voltage 1900V with thin N- thickness of 155um. The experimental results demonstrate that the use of a semi insulating material such as SIPOS, for the passivation of a planar junction termination results in stable blocking voltage characteristics. Without using wafer grinding, backside phosphorous implantation, laser annealing and using deep diffused phosphorus wafers demonstrated that it is possible to get low Vf 1.8V with low Irm and smooth reverse recovery with no ringing. Using deep diffused phosphorus wafers, optimising N- thickness and lifetime killers it is possible to get more economical and highly reliable FRDs. The same technology and fabrication procedures are potentially suitable for medium voltage 1700V to 6500V by adjusting the VLD design. Optimal solution for the area efficient VLD design can be obtained within several days of simulation.
 Heinzea B., Lutza J.,Felslb H.P., Schulze H.J., "Ruggedness Analysis of 3.3kV High Voltage Diodes Considering Various Buffer Structures and Edge Terminations ", Microelectronics Journal Vol. 39, p. 868-877 (2008).
 Lutz J., Baburske R., Chen R.M., Heinze B., Domeij M., Felsl H.P., and Schulze H.J., "The nn+ junction as the Key to Improved Ruggedness and Soft Recovery of Power Diodes, IEEE Transactions on Electron Devices ", Vol. 56, No. 11, p.2825-2832 (2009).
 Felsl H.P., Heinze B. and Lutz J., "Effects of Different Buffer Structures on the Avalanche Behaviour of High Voltage Diodes Under High Reverse Current Conditions ". IEE Proc.-Circuits Devices Syst., vol. 153, No.1, p.11-15 (2006).
About the Author
J.V. Subhas Chandra Bose worked at StarPower Semiconductor Ltd.
Hua Shen received his MS Applied Science degree at Yale University, then Doctor of Philosophy in the field of Materials at Massachusetts Institute of Technology. He is the CEO of StarPower Semiconductor Ltd.
Fu Yong worked at StarPower Semiconductor Ltd.
Bruce Chen worked at StarPower Semiconductor Ltd.