Tech Insights

Six for SiC – or is it too soon?

January 01, 2016 by Roger Kinnear

This article discusses the best time to switch from 4 to 6-inch wafers for the fabrication of Silicon Carbide (SiC) power semiconductor devices.

There is much discussion within the industry regarding when is the best time to switch from 4 to 6-inch wafers for the fabrication of Silicon Carbide (SiC) power semiconductor devices. Let me declare upfront that at Ray-theon UK’s Glenrothes plant we are currently processing 4-inch wafers – Si and SiC - but that is not to say that 6-inch is not on our roadmap.


Production of SiC semiconductors

The production of SiC semiconductors is expected to follow a similar path to Si during the 1970s and 1980s, when demand drove suppliers to continually reduce their per-chip manufacturing costs. Switching from 4- to 6-inch proved a practical means of delivering economy-of-scale, as about twice as many die per wafer can be realised. 

However, the drivers for SiC are somewhat different. It is a more enabling semiconductor material; being a wide band gap material, its physical properties allow for high switching speeds, lower losses, high breakdown voltage and an ability to operate at high temperatures. Accordingly, there is an increasing acceptance of the benefits of SiC within a variety of sectors including power transmission, traction and factory automation. Moreover, there are undoubtedly applications – ways of further exploiting SiC’s electrical and thermal properties – that no-one has even thought of yet. 

Compared to its Si counterparts, SiC power semiconductors are seemingly far more application-specific. For instance, about a year ago Raytheon was selected by a leading automotive manufacturer to fabricate a bespoke ISO/TS 16949 compliant 650V/60A SiC MOSFET for hybrid-electric and plug-in hybrid electric vehicles.


The question therefore is: bar for a few ‘generic’ power semiconductors, will SiC devices ever need to be made in very high volumes?

Today, in addition to the base material cost of processing being higher for SiC, the cost of a 6-inch wafer including its epitaxial layer is considerably higher than for a 4-inch one. It is generally considered that the wafer price ratio needs to be 2.25:1 (6-inch:4-inch) to make full use of any cost benefits. Currently it is 3.4:1. Granted, the gap will close, but at a rate governed by demand, which itself will be a function of wafer quality, reliability and market adoption.

Also, the quality of the substrate must be significantly improved in order to fully realise the die-per-wafer increase. Leading substrate suppliers are typically quoting 90% usable die for 6-inch SiC wafers versus 98% for 4-inch.

Usable area aside, there’s also the issue of the quality of the devices being fabricated. Since most devices tend to be vertically integrated, wafer thickness must be consistent - which presents some additional concerns for the fabrication tools. Any bow or warp in the 6-inch wafer could lead to manufacturing challenges on 6-inch tools; and the doping variation of a 6-inch wafer is double that of a 4-inch wafer - and this parameter is very critical to device performance and therefore yield.


Adoption of SiC devices into systems

The adoption of SiC devices into systems will not just be governed by die cost and reliability though. Packaging is important too, particularly if one is to take advantage of SiC’s high breakdown voltage and its ability to operate at high temperatures. The packaging issues are far more challenging than they ever were for Si.

For prototype work, including multi-project wafers (MPWs) and low to medium volume runs of up to 10,000 wafers, 4-inch is currently the most cost-effective; noting that the semiconductor industry considers most power applications to be low volume compared to Si products. Or, to put it another way, true economy-of-scale will come from runs of 10,000 wafers and above, and at 100s of die per wafer you’re looking for markets in need of millions of devices. For high voltage applications - in grid or rail, for example - the demand may never be high enough to realise such economy-of-scale benefits. 


Figure 1: The adoption of SiC devices into systems will be governed by a variety factors, including wafer quality and cost, but demand will be the main driving factor for switching from 4- to 6-inch wafers.
Figure 1: The adoption of SiC devices into systems will be governed by a variety factors, including wafer quality and cost, but demand will be the main driving factor for switching from 4- to 6-inch wafers. 


As mentioned, costs will come down. Accordingly, so too will the quantities required to hit true economy-of-scale. That 6-inch wafer processing is on the way is therefore a given, and a number of 6-inch Si fabs are being purchased in readiness for 6-inch SiC processing. Indeed, it’s possible that 6-inch Si only processing may all but disappear.

However, foundry qualification is costly and takes a great deal of time, particularly if a facility’s processes also need to comply with sectorspecific standards (such as the aforementioned ISO/TS 16949 for automotive). Recruiting engineers with the appropriate processing skills and experiences takes time too.

At Raytheon UK in Glenrothes, Scotland, we have over 12 years’ experience processing SiC. Moreover, we are the longest established independent full-scale production-qualified facility in Europe - if not the world - capable of 4-inch SiC wafer processing. We also have over 50 years’ experience fabricating Si devices.

We use most of our processing tools for both Si and SiC device fabrication; where such dual utilisation is recognised as a means of reducing the cost of SiC devices. We have market-leading SiC materials knowledge, practical device processing experience and an approach to sustained production and yield improvement that position us very nicely in the market.

Our thoughts on 6-inch? We have the expertise, resources and knowledge to transition to a larger wafer size at the appropriate time. But we’re not rushing. Not when we’re able to support our customers capture their markets with reliable devices fabricated on high-yielding 4-inch wafers.


About the Author

Roger Kinnear is Raytheon UK’s Silicon Carbide Wafer Fab Manager. He has more than 30 years’ experience in semiconductor manufacturing and for the past five years has been focused on cost management, process development and yield improvement for all of Raytheon’s SiC new business developments.


This article originally appeared in the Bodo’s Power Systems magazine.