TI PowerStack Packaging Technology in Volume Production

July 27, 2011 by Jeff Shepard

Texas Instruments Inc. (TI) announced that it has shipped more than 30 million units of its PowerStack™ packaging technology, which significantly boosts performance, lowers power and improves chip densities in power management devices.

"Performance requirements for computing applications are increasing in order to enable more content such as broadband mobile video and 4G communications," said Matt Romig, Analog Packaging at TI. "At the same time, there is a need for telecommunications and computing equipment to take up less space. Through a true revolution from 2D to 3D integration, PowerStack enables TI’s customers to meet these demands."

PowerStack technology’s benefits are achieved through an innovative packaging approach where TI’s NexFET™ power MOSFETs are stacked on a grounded lead frame, using two copper clips to connect the input and output voltage pins. This unique combination of stacking and clip bonding results in a more integrated quad flat no-lead (QFN) solution.

By stacking the MOSFETs in the PowerStack approach, the clear benefit is a package reduction by as much as 50 percent over alternative solutions that position MOSFETs side-by-side. In addition to reducing board space, PowerStack packaging technology provides excellent thermal performance, higher current capability and higher efficiency for power management devices.

PowerStack is in volume production today at TI’s Clark facility.

"Clark is our newest, state-of-the-art assembly/test facility in the Philippines," said Bing Viera, Managing Director of TI Philippines. "This year, we are further expanding capacity for advanced packaging techniques in Clark, nearly doubling the site’s initial capacity by the third quarter."