Technical Article

Developing Embedded Controls using PLECSPIL

May 01, 2015 by Beat Arnet

This article presents a methodology and product to help embedded controls engineers develop and test sophisticated real-time power conversion algorithms.

MCUs containing embedded microprocessors and digital signal processors (DSPs) are found everywhere from home appliances to portable devices and automobiles. According to ARM, over 50 billion processors have been sold with ARM cores, many of them for embedded applications. In the future we expect MCUs and DSPs to become even more ubiquitous, as they simplify complex daily tasks and become indispensable in collecting and processing the “big data” we now rely upon.


MCUs in Power Conversion Applications

MCUs play a crucial role in power conversion applications. The continuous quest to make power converters more efficient, compact, intelligent, and less costly requires the use of highly sophisticated control and signal processing algorithms that can only be executed digitally. An MCU can often replace multiple discrete components, and in some cases even eliminate the need for certain sensors. The price of specialized MCUs for power conversion applications has fallen to the point that even highly cost-sensitive products, such as compact DC-DC and AC-DC power modules, benefit from their use. However, writing software for such embedded applications is not trivial.

The challenge of using MCUs in power conversion applications often arises from the difficulty of developing and debugging process embedded code. There are several reasons for this, especially in cost-sensitive applications. It is important that the limited resources of an MCU (i.e., processing power and memory) are fully utilized by the application. Consequently, there is often little room left to add debugging and troubleshooting features. Furthermore, developers are often forced to write very “compact” code, sometimes even still using assembly language, to maximize the utilization of a given microprocessor. Such code can be difficult to analyze and troubleshoot. Another challenge associated with developing and testing embedded code for power conversion is the high-speed execution of such code, often 10 – 500 kHz, to control the powerstage. This prohibits the use of traditional debuggers, which halt and stop the application and limits the applicability of hardware-in-the-loop (HIL) simulators

Principle of PIL simulation
Figure 1: Principle of PIL simulation

Processor-in-the-loop (PIL) Co-Simulation

Plexim introduced a new PIL module with PLECS 3.6 specifically geared towards assisting power electronics and embedded controls engineers to test, verify, and validate embedded code. The approach is based on joining the MCU and the PLECS circuit simulator in a processor-in-the-loop (PIL) co-simulation. In other words, actual code running on the real MCU hardware is tied to the virtual world of a PLECS model, while the execution of the simulation and the embedded code is synchronized.

In PIL mode, instead of reading physical sensors, values calculated by the simulation tool are used as inputs to the embedded algorithm. Similarly, outputs of the control algorithms executing on the processor are fed back into the simulation to drive the virtual environment. This approach can expose platform-specific software defects such as numerical overflow and casting errors.

The PLECS PIL approach is independent of how the code is written/generated and does not require the use of model-based development methods. It simply relies on probes, embedded in the code, to read, and override variables in which this PIL approach is analogous to placing test points on printed circuit boards to allow signals to be injected and measured, e.g., for in-circuit testing (ICT) or network analysis.


Nested embedded control code execution in pseudo-real-time PIL operation
Figure 2: Nested embedded control code execution in pseudo-real-time PIL operation


During PIL operation, execution of the control code must be synchronized with PLECS to allow the exchange of probe information and updates of the simulation model. During synchronization, execution of the control code is completely frozen, including all timing-related MCU peripherals such as counters. Once synchronization occurs, the control code executes at a normal speed for one complete sampling period. This concept is further illustrated in Figure 2 in the context of a multi-threaded application. The synchronization periods are identified by “stop” and “go” signals. As can be seen, the code executes in a normal and nested fashion between the synchronization steps.

This mode is referred to as “pseudo-real-time operation.” that is capable of detecting and analyzing potential problems related to the multi-threaded execution of control algorithms, including jitter and resource corruption. It also offers visibility into processor utilization for latency and margin calculations.


Applications of PIL

There are several cases that are used for PIL, as an example, at the beginning of a new power converter development, actual control code can be written and tested without the need for any control or power conversion hardware. All of the requirement for PIL simulation is the MCU on a low cost evaluation board.

The PIL approach facilitates bottom-up software development, allowing the implementation and testing of building blocks such as filters and compensators in the controlled environment of a PLECS simulation. Individually tested and validated modules can then be combined into a complete control application and, again, fully and thoroughly tested in conjunction with PLECS before being applied to real hardware. Control code only has to be written once and does not need to be duplicated in the simulation tool.

During the validation and testing phase, PIL can serve as a complementary approach to HIL. Contrary to HIL, no specialized simulation hardware is needed, and the complexity/fidelity of the simulation model is unrestricted, as it does not have to execute in true real-time. Also, as mentioned above, the PIL approach can handle very high sampling rates as are typical in low power applications. Therefore, the same plant model can be used for detailed offline analysis as well as PIL simulations. Similar to needing to maintain one control code implementation, the PIL allows the engineer to maintain and utilize a single simulation model.


Schematic of the solar inverter with anti-islanding model in PLECS
Figure 3: Schematic of the solar inverter with anti-islanding model in PLECS


The PIL approach is also far superior to the software-in-the-loop (SIL) approach with which multi-threaded operation and processor/compiler specific behavior cannot be accurately reproduced. Finally, PIL permits accessing the embedded software test points (read and override probes) at any time, without requiring code recompiling. This makes PIL simulations a powerful tool for regression testing and root cause analyses after product launch.


Peripheral Modeling and Sample Applications Using the PIL Method

In PIL mode, operation of the control code is entirely isolated from the actual digital and analog I/O of the MCU. It is, therefore, necessary that MCU peripherals, such as ADC and PWM modules, are mirrored in the PLECS simulation model.  Consequently, Plexim has released a collection of high fidelity MCU peripheral models as part of our PIL offering. These models are behaviorally identical and bit-true to the actual MCU peripherals. More information on PLECS MCU peripheral models can be found in the July 2014 issue of Bodo’s Power Systems magazine [1].


Sample Application: Three-level Solar Inverter with Anti-Islanding

Figure 3 shows the PIL method at work in a grid-tied solar inverter application. The bottom half of the PLECS circuit shows the electrical model of the plant, consisting of a PV array supplying the split DC link of a three-level inverter connected to the grid via a three-phase filtering element. Also shown is the anti-islanding test load per IEEE 1547. Consequently, this model provides a virtual test bench for all aspects of inverter control, including methods implemented to prevent unintentional islanding.

It is important to highlight that the PLECS model does not contain any control algorithms. All control code associated with the solar inverter sample application has been written in straight C language and programmed into the TI C2000 MCU. The PIL operation will run the actual embedded control code in conjunction with the above-described plant model.

The PIL block between the ADC and enhanced Pulse Width Modulator (ePWM)  peripheral models acts as the interface between the PLECS model and the MCU. It offers a simple graphical user interface (GUI), as depicted in Figure 4, presenting a list of probes (software “test points”) available to override or read signals. The PIL block extracts the list of available test points directly from the debugging information contained in the compiler-generated binary file. Therefore, manual configuration is not required to define and interpret the probes in PLECS.


GUI for the PIL block showing the list of available probes
Figure 4: GUI for the PIL block showing the list of available probes


Figure 5 shows the results of complete system simulation that can be observed once the phase-locked loop has locked onto the sensor grid voltages, the inverter is activated to supply the exact power consumed by the test load. As a consequence, the grid current drops to near-zero amps that at t=50ms the grid is disconnected in which the anti-islanding algorithm (slip mode frequency shift) detects this and shuts down the inverter. Note the entire PIL system simulation takes less than 40 seconds on a standard PC.


PLECS scope showing the results of the solar inverter with anti-islanding PIL simulation
Figure 5: PLECS scope showing the results of the solar inverter with anti-islanding PIL simulation

The PIL Approach Can Be Used from Start to Finish

The new PLECS PIL module is a powerful tool for embedded controls engineers. It facilitates the development and testing of embedded software by executing actual code on an actual MCU in the otherwise-virtual world of a PLECS model.

A standard PC running PLECS, in conjunction with an MCU evaluation board, can be turned into a complete embedded code development and validation station without the need for any specialized hardware. The PIL approach is applicable throughout the entire product development process, from concept to product release and maintenance, providing a high fidelity environment, with no practical limits to the sampling frequency of the embedded code under test.

The PIL simulation can be used to expose and analyze potential problems related to the multi-threaded execution of control algorithms, including jitter and resource corruption. The approach is independent of how the control code is generated and equally applicable to hand-coded or generated code.


About the Author

Beat Arnet works as the General Manager North America at Plexim since June of 2012. He is highly skilled in the field of power electronics, electric vehicles and engineering management as well. Throughout his career, he already accomplished 5 patents. He earned his Ph.D. in Electrical Engineering at the Swiss Federal Institute of Technology Lausanne (EPFL).



  1. Prausse, F.; Ahmed, M., “Efficient Microcontroller Peripheral Modeling with PLECS”, Bodo’s Power Systems, July 2014 Issue, pp. 34-37