Technical Article

# Designing for Zero Standby Power Below 5mW

September 09, 2015 by Michael O'Loughlin

## This article offers methods of designing power supply achieving zero standby power by using primary-side regulated flyback converters.

The electronic devices created in Edison’s day were not as power-efficient as they are now. However, when they were not in use, they did not use or waste any power. That’s because a mechanical switch was used to turn them off, thus dissipating zero power when not in use.

Today, most appliances, phone chargers and other electronic devices do not have a mechanical switch. Therefore, they dissipate power unnecessarily when idle. Energy agencies in many countries have mandated legislation to limit the amount of standby power that electronic devices can dissipate when idle to help conserve energy. Depending on the rated output power, country standards and end application, electronic devices being manufactured need to have less than 500 mW down to 75 mW of standby power. However, wouldn’t it be better if these devices dissipated zero standby power when not in use?

While zero standby power is impossible to achieve without using a mechanical switch or unplugging the device, offline power converters with less than 5 mW of standby power are being designed and built today. These new power converters are being marketed as having zero standby power. Achieving less than 5 mW of standby power is possible when using primary-side regulated (PSR) flyback converters in low-power offline applications (Figure 1).

Figure 1: Schematic of an offline PSR flyback converter

One reason that the PSR flyback is a good choice for zero standby power is because the PSR control scheme senses (VS) the output voltage (VOUT) through the transformer’s auxiliary turns ratio (NA/ NS). This technique eliminates the need for TL431 optoisolator feedback circuitry. Removing the optoisolator feedback circuitry reduces your design’s standby power by 2.5 to 5 mW. This reduces the system’s standby power, making it easier to achieve zero power requirements (<5 mW). Equation 1 describes the mathematical relationship between VS and VOUT.

$\dpi{120}&space;\large&space;VS&space;=&space;\frac{\frac{N_A}{N_S}&space;\times&space;(V_{OUT}&space;+&space;V_{DG})&space;\times&space;R_{S2}}{R_{S1}&space;+R_{S2}}&space;\&space;\&space;\&space;\&space;\&space;(1)$

Some offline PSR flyback converters/controllers use a trickle-char resistor (RT) for to initially charge the power-supply controller’s bias capacitor (CVDD) at power up. The only problem with this technique is that the trickle-charge resistor dissipates power when the power supply is idle. Power supply designers generally select RT and CVDD to meet startup and system holdup requirements. RT is generally 5 MΩ and can easily dissipate more than 5 mW, with 115-V root-meansquare (RMS) input when the power supply is idle.

To achieve zero standby power, I recommend developing smart startup circuitry or using a controller, such as the UCC28730, which has this circuitry internally. This green environmentally friendly startup circuitry only dissipates power while charging the CVDD capacitor. It turns off once the power-supply switching has begun and when there is enough energy in the auxiliary winding (NA) of the transformer (T1) to power the power supply’s controller).

PSR controllers use a combination of valley switching; frequency modulation (FM) and primary peak current (IPP) amplitude modulation (AM) to control the duty cycle of the quasi-resonant/discontinuous flyback converter. This improves overall system efficiency and reduces standby input power. See Figure 2 for a functional schematic for this type of flyback controller.

Figure 2: Functional schematic of constant voltage/current flyback controller

Figure 3 describes the frequency (fSW) and primary peak current amplitude (IPP) modulation by the flyback controller’s constant voltage/ constant current flyback controller, based on changes at the controller’s voltage error amplifier (VEA) output. The transformer’s primary inductance is selected so that the converter operates at a maximum switching frequency (70 to 80 kHz, 83.3 kHz maximum). As the load decreases and less duty cycle is required, the VEA output decreases; this causes the device’s voltage-controlled oscillator to decrease the converter switching frequency, running the converter deeper into discontinuous mode. This reduces the FET’s (QA) switching losses (PSW) with decreased loading, which improves the system’s overall efficiency and reduces input standby power.

Figure 3: Control law of a controller with variations in VEA

To avoid audible noise when the VEA operates between 3.55V and 2.2V, the controller will operate at a fixed frequency of 28 kHz and adjust the converter’s duty cycle by linearly modulating the amplitude IPP. The amplitude of IPP in this fixed-frequency operation linearly adjusts down from its peak value to one-third of its peak value. This adjustment decreases the energy stored in the transformer, thus decreasing the amount of energy available to produce audible noise at switching frequencies below 20 kHz. As the converter demands lower and lower duty cycles, when VEA output drops below 2.2V, the controller once again decreases the switching frequency all the way down to 32 Hz, reducing idle power-switching losses.

Equation 2 describes the switching losses of the FET’s QA (PSW(FSW)) in a PSR flyback converter. IDS is the FET’s peak drain-to-source current, where VDS is the voltage across the FET just before it is turned on. COSS is the FET’s average drain-to-source capacitance, VG is the voltage level that drives the FET and QG is the gate charge at VG. Equation 2 shows that decreasing the frequency reduces FET switching losses. When the converter is idle, operating around 32 Hz, the switching-power losses of the FET will be more than 2600 times smaller than they would have been operating at the maximum switching frequency of 83.3 kHz.

$\dpi{120}&space;\large&space;P_{SW}(f_{SW})=\frac{C_{OSS}(V_{DS})^2&space;\&space;f_{SW}}{2}&space;+&space;\frac&space;{1}{2}&space;V_G&space;\cdot&space;Q_G&space;\cdot&space;f_{SW}&space;\&space;\&space;\&space;\&space;\&space;(2)$

Meeting low standby power also requires paying special attention to the selection of bulk, filtering and electromagnetic interference (EMI) capacitors. Select capacitors with the lowest leakage possible to ensure that you hit your standby power goals. In higher-power applications, you may want to consider some intelligent power management within your design, such as turning off a power factor corrected (PFC) pre-regulator or bypassing your EMI filter network when the converter is idle to reduce the converter’s standby power.

## Conclusion

You can use PSR flyback controllers to meet zero standby power (< 5 mW) by using PSR control techniques that remove the need for optoisolator feedback circuitry and reduce switching losses when the converter is idle. In higher-power applications, smart power management may be necessary to reduce loading when the electronic device is idle.

As a power supply designer, you will want to carefully review the datasheet of the PSR controller to ensure that the switching frequencies can go low enough to reduce switching losses to meet this zero power standby requirement (< 35 Hz recommended). I also recommend selecting a PSR controller with low standby current and smart/green startup circuitry that does not require a trickle-charge resistor and only dissipates power at initial powerup.

### About the Author

Michael O'Loughlin works as the Senior Systems Applications Engineer at Texas Instruments since October 2012 where he is responsible for technical training and the development of prototype power supplies, applications notes, magazine articles and software design tools in the area of switch-mode power supply  (SMPS) design. He earned his Bachelor's Degree in Electrical Engineering at the University of Massachusetts Lowell. He has already achieved 36 publications and have filed 2 patents throughout his career.

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