Cascode Switches the Fast Route to Higher Efficiency
This article offers discusses the cascode switches which is the fastest and most cost-effective way to improve the efficiency of SMPS.
The quest for higher efficiency as well as the appearance of power SiC and GaN JFET’s have revived the cascode switch which offers the fastest and most cost-effective way to improve the efficiency of SMPS.
Please refer to the preceding article for an introductory description of the cascode in the March issue of Bodo’s Power Systems. A cascode consists in the most general terms of the ac series connection of a grounded emitter/source and a grounded base/gate stage. The name is a combination of “cascade” and “pentode” because its output impedance is extremely high. The two transistors of a cascode constitute an “ideal” transistor because the cascode combines the best properties of a grounded-source and a grounded-gate stage. It is the optimum solution from lf to GHz, and, realizing that any switch is nothing else but an overdriven amplifier the fastest amplifier yields the fastest switch. They are extensively used in hf, wideband amplifier and pulse circuits and also early as switches. For some reason or other they did not find as yet that widespread use in power electronics they deserve.
Cascodes can be constructed of all combinations of all active components. Cascodes of dissimilar components are called “hybrid”; e.g. Si MOSFET/ JFET cascodes are hybrids. Two transistors of different polarity allow the construction of so called “folded” cascodes; input and output may be on the same potential level.
The physical function of circuits is best understood if one first assumes an ideal behaviour and corrects for the deviation from the ideal later. An ideal transistor is characterized by an infinite collector/ drain output impedance, zero emitter/source impedance and infinite gain. This holds for bipolars and FET’s; only the output impedance of JFET’s is fairly low. A collector/drain is thus a current generator, an emitter/source an ac virtual ground as an input (e.g. here) resp.a voltage generator if it is an output (e.g. emitter/source follower). Any number of current generators can be connected to a virtual ground without interference, the output will be the sum. In the following only FET’s are considered. More precisely, the source impedance of all active elements is equal to 1/S, S representing the transconductance diD /dVGS which is dependent on the operating point. S is very high for bipolars and power FET’s, so 1/S ranges from fractions of an ohm to several ten ohms which is close enough to an ideal zero.
The basic grounded-source stage with a load impedance at the output suffers from Miller effect. While a switch changes state from one extreme state (cut-off) to the other (fully turned on) it has to cross its linear range in which it is an amplifier. Miller effect is a highly unwelcome negative feedback, originating with every amplifier, if there is an impedance between output and input. In most cases it is only a capacitance. While the left side of the capacitor sees the input voltage, the right side sees the (mostly inverted) amplified input voltage, hence, in total, the capacitor sees (1 + gain) times the input voltage, so the current through it is also multiplied by that factor. The effect is the same as if there were a fictitious capacitor at the input of the size (1 + gain) x Coutput to input , called the “Miller capacitance”. The general formula: CMiller = (1 - gain) Coutput to input requires the gain to be entered with its appropriate sign, because, e.g. with a source follower, the effective input capacitance will be decreased, with an ideal follower (gain + 1) it is reduced to zero. Precisely speaking: a negative gain means that the driver has to deliver more current while a positive gain means that there is positive feedback resp. energy fed back from output to input. This causes a negative real part of the follower input impedance; if there is some inductance in the input the circuit will oscillate unless sufficient damping is provided.
The charging current for the input capacitance is equal to I = C x dv/dt. While the nearly constant gate-source capacitance has to be charged anyway, the additional charging current for the Miller capacitance is mostly much higher. Typically, the output-input (reverse) capacitance of a power MOSFET is much smaller than the input capacitance, however, the transconductance S and hence the gain are very high. This is the reason why the rise of the gate voltage is slowed down markedly as soon as the linear region is reached, often called the plateau, because all the current the driver can deliver is needed for the Miller capacitance. As soon as the gain drops when the linear region is left, the gate voltage rises again steeply. If short rise times are desired, expensive high current low-impedance gate drivers are necessary, otherwise the gate voltage rise time can extend far above 100 ns.
Here the cascode comes in: The lower drain sees the ac virtual ground source impedance of the upper FET, hence its ac drain current does not develop an ac voltage, the voltage gain is zero, hence there is no Miller effect. In fact, the advantages of the cascode regarding the driving requirements are threefold: 1. The input capacitance equals only the sum of the gate-source and drain-gate capacitances. 2. Instead of an input capacitance in the nF range and a high Miller capacitance of a husky (hv) MOSFET only the very much lower capacitance of a small 30 to 80 V ordinary MOSFET has to be driven. 3. The deleterious effect of source inductance which counteracts the gate drive is reduced because the gate current is so much lower, on the other hand it is faster. This speeds up switching and yields at the same time a cost savings, because a cascode can be driven out of standard SMPS ic’s or standard CMOS. Weak drivers can be boosted for a few cents by adding a complementary emitter follower, standard small signal types like BC 327/337-40 (807/817) switch in a few ns. Also, last not least, the small lv MOSFET may be a low-threshold type, i.e. it needs only 5 V or even less, which, by the way, is equivalent to a higher S. Hv MOSFETs for offline SMPS can not be made for 5 V drive.
The upper transistor as a grounded-gate stage just passes the ac current of the lower one along to the output; therefore, in case of a bipolar, its much higher alpha or transit frequency applies. The stage does not amplify; this may surprise at first sight and raise the question what it is good for. The purpose is to eliminate the detrimental effects of a drain ac voltage on the grounded source stage, it also effectively separates input and output, it places so to speak a shield between both.
The fast switching of the cascode comes about because, at turn-on, the low resistance of the lower FET (some ten milliohms) pulls the upper source to ground while the gate is hooked up to a fixed voltage which is at ac ground. At turn-off the small FET turns off immediately, and the high switch current charges the low node capacity fast, when it reaches about 10 V, the upper FET will be turned off, no matter whether MOSFET or JFET. With direct drive only a very low impedance, fairly expensive CMOS driver could match the cascode as far as switching speed is concerned.
Consequently, the ac properties of the cascode are determined predominantly by the lower transistor. This is also the reason why cascodes made of a Si MOSFET and a GaN JFET make no sense as normal unipolar switches, any other FET or even a fast bipolar in place of the GaN JFET will be as good. It is important to realize that the output impedance of the lower transistor functions as a feedback resistor in the source of the upper one raising the cascode’s output impedance towards infinity. It is, therefore, possible to achieve very high stage gains: Gain = Slower x load impedance; in other words: the cascode achieves the highest gain x bandwidth product attainable in a single stage.
The connection between both transistors carries only current, there is no ac voltage, hence the capacitance to ground is ineffective, but the inductance is critical. The real part of the input impedance of the upper transistor may be negative, hence the stage may oscillate at very high frequencies. While the connection should be short, the two transistors must be placed sufficiently apart in order to minimize Miller effect around the stage The cascode is not limited to two transistors, several upper transistors may be stacked on top of each other in order to sustain higher voltages.
Cascode switches in particular
Cascode switches have been used in SMPS, e.g. in the 80’s, consisting of two bipolar transistors or a small Si MOSFET and a hv bipolar, also in combination with switch-mode ic’s: a lv power bipolar in the ic and an external hv Si MOSFET made up the cascode. Hv bipolars suffer from very low current gain and are tricky to drive directly. Today’s cascodes consist of a small lv Si MOSFET and 1. a hv Si MOSFET or Coolmos, 2. a SiC or GaN JFET. There are also SiC MOSFET’s, but their gate-to-source voltage spec of - 6 V is too low for cascode operation. Obviously, the renewed interest came about as it is the only practical way to use the new power JFET’s in SMPS, with the additional advantage of much higher speed at no cost than achievable from direct-driven JFET’s. The second reason is the drive for higher efficiency which has become a major issue, norms prescribe minimum efficiencies - sofar only for external SMPS, but it is only a question of time and these requirements will be extended to cover all. JFET’s are the most natural components to be made of SiC and GaN, they are free from enhancement type gate oxide problems with their questionable reliability and are free from parasitic components. The SiC MOSFET’s on the market are primarily addressed to the huge lf Si IGBT market because they allow operation at higher frequencies with the benefits of saving cost and bulk of the passive components, also they are probably more reliable. Due to their high capacitances they can not replace Si MOS or Coolmos at regular SMPS frequencies > 100 KHz, whereas Si MOS/SiC JFET cascodes shine.
In the author’s opinion cascodes with SiC JFET’s are preferable to GaN for several reasons: 1. SiC JFET’s are an established, highly reliable technology. 2. 1200 V non-avalanche-proof components are comparable to 650 V avalanche-proof Coolmos; 1200 to 1700 V and much more has been standard with SiC for years, GaN with > 600 V has not been available sofar. 3. GaN is mostly on Si and thus lateral; SiC is thermally better off. 4. As explained it is the lower FET which determines the properties of a cascode, the upper FET’s will mainly differ only in RDSon and output capacitance. GaN hv parts with lower resistance than SiC have not been available. In fact, while 19m ohm Coolmos in TO-247 is a reality, no GaN part with less than 25 mohms is on the market although on resistances “orders of magnitude lower” were announced. These cascodes are ideally suited for bridge circuits. The claims of those manufacturers presently offerring GaN cascodes pretending this was new and only feasible with GaN JFET’s are unfounded, any other Si MOS/ JFET cascode has the same properties, irrespective of the material Si MOS/SiC JFET cascodes will become a serious contender for Si Coolmos, either directly driven or in cascode, especially for higher power SMPS and related circuits. SiC JFET manufacturers should seriously consider to offer one-piece components.
Which are the main parameters affecting efficiency, and how do they pertain to cascodes?
- Efficiency depends e.g. on the relationship of the sum of rise and fall times to the period of the operating frequency, hence one way of improvement is the shortening of the switching times. Changing from a single transistor to a cascode is the simplest and least expensive method because the additional small Si MOSFET is cheap. As mentioned, if Si MOS/Si Coolmos cascodes become available in one package, only the 4th pin has to be connected to + 12 via an RD combination. Si MOS/JFET cascodes with 3 pins can even be directly inserted in place of a single transistor. Naturally, the improvement by faster switching times will the the greater the higher the operating frequency is.
- Raising the operating frequency beyond the optimum range of 100 to 250 KHz for offline SMPS impairs efficiency. Simple low voltage buck converters may operate far into the MHz range. Also a high operating frequency is no value of its own, no customer is willing to pay for it. Losses increase in all active and passive components, mostly more than linear. In principle, the passive components become smaller at higher frequencies, but their losses rise which is only partly offset by the size reduction. While high quality ceramic capacitors can be used into the high 100 MHz range, film capacitors or electrolytics find soon their limits in the hundred KHz region. Inductive components use ferrites, the best MnZn ferrites allow flux densities up to 0.3 T only in the optimum region, there are types optimized for higher frequencies, but the flux densities have to be drastically reduced. There are more restrictions: emi norms are independent of the size resp. output power of a SMPS and limit emissions sharply, starting at 150 KHz, between 500 KHz and 5 MHz they are strictest; the upper limit has been shifted from 30 MHz to 5 GHz. With regard to this it is advisable to stay with the operating frequency just below 150 KHz, so the third harmonic stays just below 500 KHz.
With cascodes switching times down to a few ns are achievable even in high voltage switching, 5 to 20 ns are typical, but even with a careful layout emi will suffer, secondly short times imply high hf currents which stress all components including the e.c. board material; the common FR-4 has high hf losses and can heat up considerably, especially if conductors on both sides and the material constitute a capacitor; this is often not recognized because the heat generated by SMD components is also sent into the board.
Some aspects resp. advantages which are less obvious:
- A precondition for fast switching, however, is insight into the properties peculiar of the transistor type used. With standard hv power Si or SiC MOSFET’s there is a limit to the dv/dt at the drain, if it is exceeded there is danger of turning the parasitic npn on which leads inevitably to destruction. MOSFET’s proper are free from second breakdown, but they only come with the npn. It is also very dangerous to turn the parasitic diode on which is nothing else but the basecollector diode of the npn; if charge carriers are left they may turn the npn on. Literature about Coolmos says that the npn can not be turned on. With unipolar switches it is sometimes necessary to place a fast diode with its anode at ground in parallel to the switch. JFET’s are free from parasitic elements, do not suffer from second breakdown, but lack an avalanche rating; in case of overvoltage, there will be an ordinary D - S diode breakdown. This implies that they must not be tested for breakdown voltage, because one breakdown equals destruction!
- Hv MOSFET’s “kick back”, i.e. current comes out of the gate during turn-off, this can destroy bipolar and CMOS ic’s, because the strict rule has to be obeyed that under no circumstances any input or output must be pulled more than 0.3 V below ground or above the actual (not nominal!) supply voltage, otherwise parasitic transistors or/ and thyristors may be turned on. This can only be prevented by two husky Schottky diodes across the driver output. This is a dangerous trap, because not all ic manufacturers point to the necessity of such Schottky clamps - or only later in an app note. Of course, depending on the fabrication method, some ic’s are more susceptible than others. This old problem is prevented by a cascode, because at turn-off the current is diverted into the node capacitance as described, the drain of the lower FET does not see the several hundred volts on the output drain, but only a few ten volts, also, the reverse capacitance of the small FET is much lower than that of the hv FET. Hv Si MOSFET’s don’t look at all inside as simple as the symbol pretends: readers are referred to the AppNote no. AN7260.2 of Sept. 1993 “Power switching waveforms, a new insight” of Harris Semiconductor which contains one of the best descriptions. Of course, this does not apply to all manufacturers’ MOSFET’s.
- Circuit rise and fall times are only partly determined by the switch, the capacitances given in the data sheets bear little meaning in practice. A minimum of two components are connected to any switch, e.g. in a PFC the choke and the diode; in most other circuits there are more, e.g. damping elements. Consequently, any changes in the switch’s output capacitance become only partly effective. The output voltage rise time after turn-off depends mainly on the current the particular circuit is able to deliver to charge the capacitance. In a PFC, e.g., this current is limited by the choke and the voltage at its lefthand terminal. If fast switching is intended, simple and cheap chokes will not do, because also the choke’s distributed capacitances have to be reduced by a suitable winding construction. SiC diodes outperform all other diodes, but their capacitances are fairly high, on the other hand. Therefore the improvement in switching times is often mainly seen during turn-on, i.e. in the output voltage fall time
How to design your own cascode
As long as there are no Si MOS/Si Coolmos or Si MOS/SiC JFET (for appr. > 1 KW) cascodes available as one-piece components, designers will have to resort to designing their own. On the other hand this allows maximum flexibility. This chapter is a guide to the practical design. Because cascodes excel especially in high voltage switching (offline SMPS), this application is chosen here. Exchanging a single MOSFET or Coolmos for a cascode is the quickest route to increased efficiency; all that is needed is a small inexpensive Si MOSFET and a few penny parts.
Selection of transistor types
The upper (hv) transistor is either a 650 V Si Coolmos (Infineon designation, others use the term super junction) or a 1200 V SiC JFET; this switch will be appropriate even for flybacks. If the switch is destined for a PFC, a 600 V Coolmos or SiC JFET will do, here the CP series is best. As outlined above, the properties of the cascode are mainly determined by the lower transistor, hence it is by no means necessary to select the latest hv types, most older types like Coolmos C3 will do as well, offer lower prices, more second-sources, and, last not least, the chip sizes will be larger, improving RTh , heat transfer and the resistance to short overloads! The latest Coolmos have only half the size of the former chips, as is obvious from the Rth spec of 2 degr./W. If the task is to raise the efficiency of an existing SMPS, the Si Coolmos used sofar can remain in most cases.
In selecting the lower Si MOS transistor resist the temptation of using a low RDSon type! As the total on resistance of the cascode is predominantly determined by the upper one’s RDSon , it is fairly immaterial whether the lower one is a 1, 10, 20 (or more) mohms type. A relationship of 10 : 1 seems quite adequate. If the upper one is specified for 200 mohms, the lower one will be fine with 20 mohms, considering tolerances and the increase when warming up. As the power dissipation in the lower transistor will be low, a SMD type will suffice.
The higher RDSon types offer much lower capacitances and higher D - S voltages. How much voltage will it have to take? At first sight, the highest voltage on its drain will be the pinch-off voltage of the upper one in case of JFET’s and the gate voltage in case of MOSFET’s, typically 12 V. The upper one will act as a source follower with respect to the drain of the lower one, but this is only true steady-state. See below.
Figure 1 shows the completed circuit. RD combinations are required. The value of the resistor depends on the input capacitance of the respective transistor and is typically between 10 and 100 ohms. It is necessary in order to dampen oscillations, but increases the turn-on time resp. lengthens the output voltage fall time; if it is too small, strong oscillations in the hundred MHz region will show up, depending on the parasitic inductances and capacitances within the circuit. They stress the components and cause emi. The resistor also limits the turn-on gate current. One should stay rather on the high side.
The diode conducts the current out of the gate during turn-off past the resistor, here, a 1 N 4150 (not 4148) is sufficient even for fairly large chips, it takes several amps of peak current for some μs. This bypass diode also limits the voltage drop across the resistor caused by the turn-off current.
The RD components must be placed close to the gate terminals, and a ceramic capacitor directly to ground. The board layout must be such that the cascode is located immediately next to the choke or transformer, absolutely minimizing the length of conductors in the whole circuit. The hf current return path will usually run through a capacitor back to the source. Electrolytics should be bypassed and saved from hf currents by placing PP or PE film resp. high quality ceramic capacitors in parallel, no worse material than X7R. It is important to keep the lower gate (input) apart from the upper drain (output) in order to prevent Miller effect; the two transistors may be set a bit apart if the separation can not be achieved otherwise.
An important aspect in cascode design is seldomly mentioned: the behaviour of the internal node, i.e. the connection of drain and source. When the lower one turns off, the current coming out of the upper one is diverted into the node capacitance. A MOSFET as the upper one will be cut off as soon as its source voltage comes within about 2 V of the fixed gate voltage. In order to turn off a nJFET with its gate at ground, its source must rise above the pinch-off voltage which will be also around 10 to 12 V. However, because the upper one needs time to turn off, the node voltage will overshoot easily up to, e.g. to 80 for some ten ns, which stresses the gate oxyde resp. the gate-to-channel diode much above their limits. The drain voltage of the lower one must hence be chosen adequately high in order to prevent breakdown, in practice between 30 to 80 V. As a rule, a diode plus a zener diode between source and gate or a zener between the node and ground are necessary, its value chosen so that the maximum gatesource spec is obeyed. Very short spikes can be ignored.
Unless the SMPS is a low power unit, the upper transistor must be properly cooled. Two important items are often disregarded. TO-220 and similar styles must not be screwed or riveted to the heat sink, but only mounted with a suitable spring clamp on the body, otherwise they will loose thermal contact with time, overheat and be destroyed. The importance of the insulating material is often not recognized. In the first place, for most materials, the permissible voltage decreases sharply with rising frequency; the popular polyester can take only 10 % of the 50 Hz voltage at 100 KHz! Depending on the safety class the insulation must withstand up to 4 KVrms. But apart from the isolating function the insulator is the dielectric of the capacitor consisting of the transistor metal housing and the heat sink. The more hf current is injected into the heat sink, the more emi is created which is difficult and costly to keep within the limits of the norms. The capacity must hence be minimized, that is a low dielectric constant is required. But the material should also have low dielectric losses. In practice it is not possible to find out how much heat is caused within the insulator because the transistor also becomes hot. Ceramic-filled silicone rubber is a preferred material of reasonable cost; >= 0.4 mm material is advisable for lower capacitance and considering the softness of the rubber. Beware of materials not specifically designed for that purpose, e.g. Kapton is our best insulator but its thermal conductivity is extremely poor.
About the Author
Dr.-Ing. Artur Seibt is a professional electronics design lab consultant with specialization in SMPS with 40 yrs. experience incl. SiC, GaN, D amplifiers. Inventor of current-mode control (US Patent) and He is also an expert in EMI design.