Tower Semi and Triune Systems To Collaborate On Power Management Platform
Tower Semiconductor Ltd., an independent specialty foundry, and Triune Systems LLC, an IC design and test development provider, announced an agreement to collaborate on developing what they describe as the most complete power management platform in the industry.
Through this collaboration, the companies will jointly design and develop intellectual property (IP) for Tower’s 0.18µ Bipolar-CMOS-DMOS (BCD) process to deliver a family of low and high voltage power management products and IP for a variety of applications to enable faster design cycles and lower cost designs. In particular, the companies will design and develop zero mask adder non-volatile memory blocks, based on Tower’s patented Y-Flash technology, suitable specifically for 5V operation on high voltage platforms. High volume production for the co-developed high voltage power management products is expected to commence in the second half of 2009.
"As a Tower-Authorized-Design-Center, Triune Systems’ expertise in design and IP development will further enhance our power management platform to allow for faster design cycles and lower cost designs," said Dr. Avi Strum, Specialty Business Unit Vice President, Tower Semiconductor. "The collaboration with Triune Systems and its contribution to the design of the scalable Y-Flash based NVM blocks will complement our business strategy and core competencies in the consumer, medical, industrial and automotive markets."
"Based on Triune Systems’ experience in power management IP development, we believe the Tower BCD process offers great flexibility along with cost effectiveness. Specifically, the integration of cost-effective NVM into the Tower BCD process provides significant differentiation which will enable the enhancement of power management solutions. We are looking forward to leveraging the strengths of both companies," said Ross Teggatz, President of Triune Systems.
Tower’s .18µm/.5µm Bipolar-CMOS-DMOS (BCD) process platform is highly modular offering a very dense 5V-only option on .18µm design rules, a Low Rdson LDMOS portfolio with 5V gate drive capability, and up to 60V operating with an 80V breakdown voltage. In addition, there is an option to add dense .18µm CMOS fully compatible with Tower’s .18µm CMOS platform, including a cell library, I/Os, and complex IP blocks. The process comes with a full suite of analog components including complementary bipolar, MIM caps, high sheet resistors, Zeners and Schottky diodes. Tower provides embedded non-volatile memory (NVM) on its power management BCD advanced logic process with full flash capability from 32 bit to 1 mega bit at no additional cost in process complexity (mask count). Triune Systems is also collaborating with Tower on the design and qualification of NVM blocks that utilize this proprietary technology. Array sizes are up to five times smaller than other competitive solutions and can be built using only one gate oxide allowing for ultra low cost designs.
