International Symposium on Power Semiconductor Devices and ICs—ISPSD 2018

Gary M. Dolny at Bodo's Power Systems

The 30th Annual International Symposium on Power Semiconductor Devices and Integrated Circuits, (ISPSD) was held from May 13-17, 2018 in Chicago, Illinois, USA. ISPSD, which is sponsored by the IEEE Electron Devices Society (EDS), and technically co-sponsored by the IEEE Power Electronics Society (PELS), Industrial Applications Society (IAS), and Institute of Electrical Engineers of Japan (IEEJ) is considered the world’s premier forum for scientific and technical discussions in all areas of power semiconductor devices, power integrated circuits and packaging.

This year’s conference brought together over 450 attendees from around the world as well as many exhibitors from fields related to power semiconductors including test equipment, design software, and wafer foundries. Each year the ISPSD host site rotates between Europe, Asia, North America, and a developing country. This year’s venue was the historic Palmer House Hilton Hotel located in the well-known loop area of downtown Chicago within walking distance of numerous shops, museums and other points of interest.


ISPSD 30-Year Anniversary

2018 marked the 30th anniversary of the ISPSD. Conference General Chairman, Professor John Shen of Illinois Institute of Technology stated that since the first meeting in 1988 in Tokyo, Japan, ISPSD has been instrumental in the growth of the global power semiconductor industry. He noted that more than 1600 papers have been presented over the past three decades and that most of the breakthrough power device technologies were first reported at ISPSD before they were introduced commercially. These breakthroughs enabled the global power semiconductor industry to grow into a $30 billion market, facilitating applications such as solar power, wind power, electric vehicles, lighting and industrial drives. As part of the anniversary celebration, 32 distinguished members of the power device community were inaugurated into a newly established ISPSD Hall of Fame during the Wednesday 30th Anniversary Celebration Banquet.


Figure 1. Newly inducted members of the ISPSD Hall of Fame


ISPSD Technical Programs

The conference technical program consisted of 17 technical sessions devoted to both silicon and wide-bandgap discrete power devices, power IC’s, packaging technologies and novel device structures. The sessions were made up of 50 oral and 79 poster presentations selected from 245 abstracts submitted from 23 different countries.

The conference began on Sunday, May 13 with a full day technical short course taught by various experts in the field. The short course was designed to educate both students and working professionals on topics of current interest as well as introducing emerging technologies. This year’s short course topics included Advanced Silicon Technologies, Loss Mechanisms in Silicon and Wide-bandgap Power Devices, Silicon Carbide Device Design and Applications, Vertical Power Electronics Based on GaN, AlGaN/GaN Device Reliability, and Multi-Chip Power Module Design.

The technical sessions opened on Monday, May 14 with four invited plenary presentations. The first by M. A. Shibib of Vishay Siliconix, L. Lorenz of ECPE, and H. Ohashi of NEPRC was titled “ISPSD-A 30 Year Journey Advancing Power Semiconductor Technology” [1]. The paper reviewed the history of ISPSD and highlighted the most important contributions that the conference has made to the power semiconductor field. A second, by L. Spaziani of GaN Systems, was titled “Silicon, GaN, and SiC—There is Room for All, An Application Space Overview of Device Considerations” [2]. The presentation considered the general system's priorities such as power density, efficiency and cost for several key applications areas for power semiconductor devices and then weighed these against the properties of the three major materials technologies.

While the wide-bandgap technologies are making steady progress the need for lower cost, wafer availability and proven reliability were identified as concerns. N. Machida of Sumco addressed “Si Wafer Technology for Power Devices: A Review and Future Directions” in the third presentation [3]. He stated that the future direction is in the increased utilization of the magnetic field applied Czochralski (MCZ) crystal growing method as well expanding the production of 300 mm diameter wafers for power applications. The final plenary presentation was given by Bert De Colvenaer, ECSEL JU and addressed “The Future of Power Semiconductors: An EU Perspective” [4] He noted that Europe and the ECSEL JU are investing in power semiconductors as a key enabling technology for achieving EU goals for increased renewable energy usage. He stated that success hinges on regulation and standards, technology availability, reliability, seamless integration, and acceptance by the users.

A number of conference presentations highlighted the steady progress being made in silicon carbide power MOSFET technology. Chowdhury et. al. from Monolith Semiconductor presented a 1200V SiC MOSFET with an improved tradeoff between on-resistance and reverse bias gate oxide electric field [5]. The improved tradeoff was obtained by optimizing the JFET doping profile and unit cell design. These MOSFETs showed a specific on-resistance of 3.5 mΩ-cm2 at room temperature, increasing to 5.9 mΩ-cm2 at 175°C. The device also exhibited excellent High-Temperature Reverse Bias (HTRB) reliability as shown by no failures after stressing at 1440V, 175°C for 1000 hours.
Han et. al. from North Carolina State University presented a novel 1.2 kV Buffer Gate SiC-NMOS structure [6]. In this device, the gate polysilicon is removed from above the JFET region, similar to a conventional split-gate structure but in addition, the buried player is extended beyond the gate edge to further minimize gate to drain charge. The devices were formed with both accumulation and inversion mode channels. Experimental data confirmed the accumulation mode Buried- Gate MOSFET has reduced figures of merit Ron×Cgd and Ron×Qgd compared with both the conventional accumulation mode SiC-MOSFET and split-gate SiC-MOSFET, due to the significantly improved Cgd and Qgd. The improvement was in the range of 2.6x to 4x.

Yen et. al. of Hestia Power Corp. demonstrated a monolithic SiC junction barrier controlled Schottky diode (JBS) integrated MOSFET (JMOS) using an identical process flow as a standard SiC double implanted MOSFET (DMOS) without area penalty [7]. To incorporate a good Schottky contact into the MOSFET cell, the Schottky openings were formed together with the openings to the gate, after the ohmic contacts were formed in the source(body) openings on the n+/p+ regions. A standard Ti/TiN/AlCu metal stack was used to form gate contacts for the gate electrode and Schottky contacts and ohmic contacts. The device provides similar on-resistance and drain-source breakdown voltage with the same chip size as the standard double- implanted MOSFET (DMOS). The reverse recovery charge at 650V and 1200V at 150°C were 22% and 53% lower than the corresponding DMOS while the peak reverse recovery current of the 650V and 1200V JMOS were 26% and 40% lower than the corresponding DMOS. The device was demonstrated to be reliable via forward current stress, surge current test, and 1000 hours HTRB.

The threshold voltage hysteresis effect in SiC MOSFETS received considerable attention. This effect is observed as a negative shift in the Id-Vg transfer characteristics that becomes more pronounced as the off-state gate voltage becomes more negative. The effect is attributed to interface states in the bandgap which can become positively charged when a negative gate voltage is applied but are neutralized under positive gate bias. The positive charges are in a direction to enhance channel inversion, thus the onset of drain current occurs at a lower value of Vgs. Peters et. al. [8] addressed this phenomenon and concluded that the effect is fully reversible, harmless for turn-on and almost irrelevant for turn-off. They also performed Bias Temperature Instability tests and showed that drift is predictable and within data sheet limits.

Unger [9] of Technische Universität Dortmund, performed an application-oriented investigation of the impact of negative off-state gate-source voltages on 600V class SiC MOSFETs. They observed that as the off-state gate voltage becomes more negative, a more pronounced drain current overshoot immediately after turn-on is observed. The overshoot decays over time as the channel current neutralizes the traps. The phenomenon especially affects the accurate determination of the threshold voltage and transfer characteristics but can also lead to a reduced short-circuit withstand time depending on the circuit operation.

SiC JBS rectifiers received significant interest despite the fact that commercial products have been available for several years. Three presentations addressed issues related to surge current reliability. Van Brunt et. al. [10] from Wolfspeed presented a study of surge current failure mechanisms in 4H-SiC JBS rectifiers. They noted that the transition between the normal Schottky operating mode, and the bipolar mode, in which the p-n junction forward biases, is a function of the dynamic heating that occurs during the surge environment and not just the electrical bias conditions. For non-repetitive transients, the energy-to-fail at 10 μs is over 10 times larger than the energy which causes a failure at 10 ms due to heat diffusion into the package. Palanisamy et. al. [11] of Technische Universität Chemnitz and Infi- neon studied repetitive surge currents in state of the art 650V, 1200V and 1700V SiC MPS diodes operating in the bipolar regime with 10 μs pulses typically 20% lower in magnitude than the destructive limit for single-event pulses. They observed that most devices could withstand a large number of repetitive pulses, typically over 1000. Observed failure mechanisms included a change in the Schottky barrier or power metal, chip cracks at the middle of the die, partial bond wire lift-off and front side metallization delamination. Xu et. al. [12] of Zhejiang University studied the surge capability of 1.2 kV SiC JBS diodes in which the p+ region is formed with a 500°C implantation step. Their surge current experiments verified that an improved capability is achieved in the JBS diodes with high-temperature implantation.

Advances in GaN technology were highlighted in three dedicated conference sessions. Posthuma et. al. [13] of IMEC and On Semiconductor described an industry ready 200 mm GaN-on-Si technology. The process features 650 V rated enhancement mode p-GaN gate HEMTS that were fabricated with an Au-free process. Source and drain ohmic contacts are realized by recess etching, cleaning, Ti/TiN/ Al-based metallization and low-temperature ohmic anneal. The threshold voltage was 2.8 V with an off-state leakage of less than 1μA/mm at room temperature. Large area power devices with gate width up to 36 mm were demonstrated. For the optimum field plate design, no key device parameters including dynamic Ron shifted by more than 10% after 1008 hours of HTRB testing at 80% of rated voltage.

Tajalli [14] et. al. of Univ. of Padova, ON Semiconductor, and CMST IMEC/Ghent University discussed the use of proton implantation for the control of dynamic Ron in AlGaN/GaN transistors. They attributed the improvement to a small increase in leakage current in the unintentionally- doped GaN layer which facilitates charge de-trapping from the buffer layer. Proton irradiation at fluences of 1.5 x 1014 cm-2 with energy of 3 MeV was shown to completely suppress dynamic Ron over the entire voltage range and up to 150°C without significant modification to other device parameters. The tested devices had a gate width of 200 mm and were designed for 650 V operation.

Riccio et. al. [15] of the University of Naples and Cambridge University analyzed the short-circuit robustness of new generation p-GaN HEMTs. Their tests were performed on commercial devices with a rated breakdown voltage of 650 V and on-state resistances of 200 mΩ and 50 mΩ. They observed a large increase in gate current, from a 40 μA typical value at room temperature to up to 9 mA during short circuit testing. They attributed this increase to a fast temperature rise within the device during the short-circuit pulse. This current imposes a voltage drop across the gate resistance which results in a reduction of the effective Vgs at the gate terminal. The combination of mobility reduction as a result of self-heating along with the effective decrease of gate drive voltage results in a drastic reduction of the drain current, thus enhancing the short-circuit capability of the device. Efthymiou et. al. [16] of Cambridge University and Vishay Siliconix investigated the effect of layout on the switching of enhancement mode, 650 V, 15 A, p-GaN gate HEMTs. Three layouts with variation in the placement of the contact pads for the different terminals (drain, source, gate) and the metallization tracks which connect the fingers to the pads were studied. The different designs were found to exhibit varying degrees of susceptibility to oscillatory behavior during high dI/dT switching. A design with peripheral drain pads and an interior source contact exhibited the highest immunity to oscillations but at the penalty of increased on-state resistance. The oscillatory behavior was found to be related to the level of source inductance and the unbalances of these inductances within the die.

Smart-power gate driver integrated circuits for use with GaN power devices were discussed in several presentations. Tang et. al. [17] of the Hong Kong University of Science and Technology and Taiwan Semiconductor Manufacturing Company demonstrated a 650-V enhancement-mode GaN power switch with a monolithically integrated gate driver fabricated on a commercial GaN-on-Si power device platform. The low-voltage logic and control circuits are fabricated in enhancement/depletion HEMTS and require no additional process steps. This monolithic integration of the gate driver circuit minimizes parasitic inductance in the gate loop and thus suppresses ringing and alleviates overshoot. This enables high switching speed in the GaN power transistor enabling reduced switching losses. Yu et. al. [18] of the University of Toronto presented an integrated smart gate driver IC for GaN power transistors. The chip featured a segmented output stage topology, programmable sense-FET, current sensing circuits and an on-chip stacked-based CPU for flexible digital control. The circuit was fabricated on a commercial 0.18 μm BCD technology and was targeted for driving depletion-mode GaN HEMTS in a cascode configuration. The circuit dynamically adjusts the gate driving strength to achieve slope control during switching, monitors the load current using a built-in sense-FET, provides peak-current regulation and actively adapts the driving pattern in less than 1 μs to optimally match the load conditions.


Resources and ISPSD 2019

The full conference proceedings will be available to IEEE Members through the IEEE Explore website.

ISPSD 2019 will be held from May 19-23, 2019 in Shanghai, China, one of the country’s most dynamic, vibrant, and diverse cities. This will be the first time in its 31-year history the conference will be held in mainland China. Abstract submission deadline on November 12, 2018. Topics of interest include but are not limited to High Voltage Power Devices, Low Voltage Power Devices, SiC, GaN, and other Wide- Bandgap Power Devices, Power ICs, and Module and Packaging Technology. More information is available at the conference website



[1] A. Shibib, L. Lorenz, H. Ohashi, “ISPSD: a 30-year journey in advancing power semiconductor technology”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 1-7.

[2] L. Spaziani, L. Lu, “Silicon, GaN and SiC: there’s room for all”, in Proceedings of 30th ISPSD, Chicago Ill., USA, May 2018, pp 8-11.

[3] N. Machida, “Si wafer technology for power devices-A review and future directions”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 12-14.

[4] B. De Colvenaer, “The Future of Power Semiconductors: an EU Perspective”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 15-23.

[5] S. Chowdhury, K. Matocha, B. Powell, G. Shieh, S. Banerjee, “Next generation 1200V, 3.5mΩ.cm2 SiC planar gate MOSFET with excellent HTRB reliability”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 427-430.

[6] K. Han, B. J. Baliga, W. Sung, “Accumulation channel vs. inversion channel 1.2 kV rated 4H-SiC buffered-gate (BG) MOSFETs: analysis and experimental results”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 371-374.

[7] C.-T. Yen, F.-J. Hsu, C.-C. Hung, C.-Y. Lee, L.-S. Lee, Y.-F. Li, K.-T. Chu, “Avalanche ruggedness and reverse-bias reliability of SiC MOSFET with integrated junction barrier controlled Schottky rectifier”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 56-59.

[8] D. Peters, T. Aichinger, T. Basler, G. Rescher, K. Puschkarsky, H. Reisinger, “Investigation of threshold voltage stability of SiC MOSFETs”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 40-43.

[9] C. Unger, M. Pfost, “Influence of the off-state gate-source voltage on the transient drain current response of SiC MOSFETs”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 48-51.

[10] E. Van Brunt, T. Barbieri, A. Barkley, J. Solovey, J. Richmond, B. Hull, “Surge current failure mechanisms in 4H-SiC JBS rectifiers”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 415-418.

[11] S. Palanisamy, J. Kowalsky, J. Lutza, T. Basler, R. Rupp, J. M. Fallah, “Repetitive surge current test of SiC MPS diode with load in bipolar regime”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 367-370.

[12] H. Xu, J. Sun, J. Cui, J. Wu, H. Wang, S. Yang, N. Ren, K.Sheng, “Surge capability of 1.2kV SiC diodes with high-temperature implantation”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 419-422.

[13] N.E. Posthuma, S. You, S. Stoffels, D. Wellekens, H.Liang, M. Zhao, B. De Jaeger, K. Geens, N. Ronchi, S. Decoutere, P. Moens, A. Banerjee, H. Ziad, M. Tack, “An industry-ready 200 mm p-GaN E-mode GaN-on-Si power technology”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May, 2018, pp 284-287.

[14] A.Tajalli, A. Stockman, M. Meneghini, S. Mouhoubi, A. Banerjee, S. Gerardin, M. Bagatin, A. Paccagnella,E. Zanoni, M. Tack, B. Bakeroot, P. Moensand G. Meneghesso, “Dynamic-Ron control via proton irradiation in AlGaN/GaN transistors”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 92-95.

[15] M. Riccio, G. Romano, L. Maresca, G. Breglio, A. Irace, G. Longobardi “Short circuit robustness analysis of new generation enhancement-mode p-GaN power HEMTs”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 104-107.

[16] L. Efthymiou, G. Camuso, G. Longobardi. F. Udrea, T. Chien, M. Chen, A. Shibib, K. Terrill “ Effect of device layout on the switching of enhancement mode GaN HEMTs”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 220-223.

[17] G. Tang., M.-H. Kwan, Z. Zhang., J. He, Ji. Lei, R.-Y. Su, F.-W. Yao, Y.-M. Lin, J.-L. Yu, Th. Yang, C-H Chern, T Tsai, H. C. Tuan, Alexander Kalnitsky, K. J. Chen, “High-Speed, High-Reliability GaN Power Device with integrated gate driver”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 76-79.

[18] J. Yu, W. J. Zhang, A. Shorten, R. Li, W. T. Ng, “A smart gate driver IC for GaN power transistors”, in Proceedings of 30th ISPSD, Chicago, Ill., USA, May 2018, pp 84-87.

Source: Bodo's Power Systems, July 2018