Freescale and UFL Create Double-Gate Transistor Model

June 01, 2005 by Jeff Shepard

Freescale Semiconductor Inc. (Austin, TX) and the University of Florida (UFL) have created what they claim is the first double-gate transistor model. The technology is expected to allow development of smaller, lighter portable devices with longer battery life, as well as faster computing devices that can handle growing graphic, video, voice and data processing requirements.

The double-gate transistor version, called FinFET, was engineered to pack more computing power into less space and reduce power consumption, while using existing semiconductor manufacturing processes. The drive to put more MOSFET transistors on a silicon chip by shrinking the dimensions of the transistors, commonly referred to as Moore's Law, faces increasing obstacles with continued shrinkage of conventional planar transistors. This is due to the difficulty of maintaining control of charge carriers moving through the transistor when using only a single gate. The double-gate transistor mitigates this difficulty by introducing an additional gate to enhance control, allowing for continued shrinkage.

In order to design a silicon chip using double-gate FinFET transistors, an adequate model of the transistor’s electrical behavior is required to simulate the intricate and highly complex circuitry on the chip. While the software model developed with the University of Florida moves the technology one step closer to commercialization, designers can now use it to develop end-user products.

Freescale is now driving licensing of the University of Florida’s double-gate models.