Fine-Grained Software-Controlled Power with Autonomous Control
Sonics, Inc. today introduced the ICE-Grain (Instant Control of Energy) Power Architecture for system-on-chip (SoC) design teams that require an automated power management solution with "worry-free implementation" at the highest level of abstraction. Sonics' ICE-Grain Power Architecture is the semiconductor IP industry's first and only complete power management sub-system comprised of configurable hardware IP blocks, embedded control software, and integrated design tool environment.
With the ICE-Grain Power Architecture, SoC designers partition their chips into much finer "grains," which enables up to 10x faster and more precise power control. Power "grains" are very small sections of an SoC that include functional logic that can be individually power controlled using one or more savings methods. A grain is connected to one or more clock domains and attached to at least one power domain, and includes defined signals and conditions for power control.
Grains are often an order of magnitude smaller than conventionally independent power or clocking domains, and multiple grains can be composed into larger hierarchical grains. The ICE-Grain Power Architecture automates the tasks of grain connection and management by synthesizing both central and local control circuitry blocks for the greatest total SoC power reduction.
Sonics is targeting the ICE-Grain Power Architecture to mainstream SoC design teams creating energy-sensitive applications in consumer, IoT, mobile, wearables, automotive, and set-top box markets. These teams typically lack the engineering resources or time necessary to develop sophisticated, highly responsive, fine-grain power management schemes. Their resulting chips often consume more energy than necessary and sometimes significantly more than the design specification allows.
For mainstream SoC design teams, the ICE-Grain Power Architecture is an automated solution providing the most advanced capabilities and benefits of sophisticated power management schemes to address critical trends such as: The number of clocking, power and voltage domains that require independent control is increasing; The number of power events that need to be processed is increasing dramatically. These events must be managed at run-time to satisfy power constraints; and Power and energy budgets are tightening and becoming more challenging, including thermal, battery, and regulatory limits.
"Sonics is keenly aware of the power problem in today's designs from our long history integrating battery-powered SoCs with on-chip networks and from our recent power research and patent work," said Drew Wingard, CTO of Sonics. "Our goal with the ICE-Grain Power Architecture is to give system architects the IP, drivers, and automation tools they need to address power reduction early in the SoC design process where it proves most effective. To save power, designers must power-down parts of the SoC as quickly as possible to eliminate leakage current, and then power the parts back up just in time. Our fine-grain approach controls power in hardware for much faster switching between states. This approach also implements dynamic voltage and frequency scaling to take advantage of the high dependence of active power on voltage."
Compared to conventional, software-controlled approaches, Sonics' fine-grain technique provides many more opportunities to turn parts of the chip to low-power states. Its hardware-controlled state transitions enable the architecture to optimize the power state to match the operating conditions of the controlled grain. This allows SoC designers to exploit many more "dark silicon" states than they can typically achieve using software-controlled approaches.
Key ICE-Grain Power Architecture features and benefits are: The first commercial technology to manage and control all common power techniques in a unified environment. Hardware identification of power saving opportunities; Unique "wake on demand" technique allows automated grain shut down and instantaneous wake up when needed; Hardware control of clock, isolation, retention, and power gating sequences; Hardware control of operating points for DVFS (dynamic voltage and frequency scaling) and AVS (adaptive voltage scaling); and Leverages existing software-controlled power management techniques.
Scalable, distributed, and modular architecture. Centralized grain controller block manages individual and inter-grain power sequencing and operating point assignment; Distributed, local controller blocks per grain handle power sequence execution and minimize the logic in the always on domain; and Hardware event control system supports hundreds of grains with predictable, low latency and virtually no impact on processor performance
Easy, worry-free implementation of hardware control and fine-grain power reduction. Scales to support hundreds of power grains that are correct-by-construction and include on-chip debug and monitoring; and Minimal area and power impact to the original design. EDA tool support complies with industry-standard tools, flows, and formats.
Complete, integrated solution; no special power expertise required. With the ICE-Grain Power Architecture, designers work at the highest level of abstraction, which means they do not have to be power management experts to adopt and use the solution; and Leverages existing power management techniques where designers can integrate some or all of their existing software-based approach
"We have followed Sonics for many years and can confirm that the company has been exposed to power issues in more than 250 chip designs," said Rich Wawryzniak, Senior Market Analyst: ASIC & SoC, Semico Research Corp. "They have applied that body of knowledge and years of power reduction development work in their on-chip network products and are now focused on solving the power problem for the broader SoC market place. There is a large market opportunity for an IP supplier that delivers a commercial solution on par with the most advanced power schemes developed by the "army of experts" at large system companies like Apple. We believe there is strong pent-up demand for an automated power management solution with chip design teams building mainstream products in more modest volumes than Apple. Sonics is well-positioned to take advantage of this opportunity."
Sonics is currently engaging with a limited number of early access technology partners who are interested in using the ICE-Grain Power Architecture for SoC design projects in 2015. Partners can implement the ICE-Grain Power Architecture independently of Sonics' on-chip networks; however, there are strong synergies when they are used together. Sonics plans product announcements related to the ICE-Grain Power Architecture in late 2015.