Enhancement-Mode GaN Transistor Reliability exceeds 10 Years

June 16, 2015 by Jeff Shepard

During the recent PCIM Europe Conference, a paper titled "Enhancement Mode Gallium Nitride Transistor Reliability" was presented by Alex Lidow, Rob Strittmatter, Chunhua Zhou, and Yanping Ma, with Efficient Power Conversion Corporation. The paper opens by pointing out that reliability testing data for GaN transistors continues to accumulate with positive results. This paper built upon previous studies, providing new reliability data on commercially available enhancement mode GaN transistors under a wide variety of stress conditions.

“eGaN FETs have been subjected to a wide variety of reliability tests for device qualification. These tests included High Temperature Reverse Bias, High Temperature Gate Bias, High Temperature Storage, Temperature Cycling, High Temperature High Humidity Reverse Bias, Autoclave, and Moisture Sensitivity. Parts were stable under the stress conditions and are fully qualified, demonstrating the robustness of these wafer level chipscale (WLCS) GaN transistors. Acceleration factor tests were conducted over voltage and temperature in order to estimate the time to failure within the datasheet operating range. Under both HTRB and HTGB type stress conditions, the MTTF well exceeds 10 years at maximum operating temperature and at both VDSmax and VGSmax. These studies have further shown that eGaN FETs are able to operate with very low probability of failures within the reasonable lifetime of end products manufactured today,” the authors stated.

They also pointed out that, “it is not possible to say that eGaN technology is significantly more reliable than silicon or SiC based on this acceleration study. However, it can be concluded that the dominant failure mechanisms for eGaN FETs, namely, RDS(ON) shift in HTRB and gate induced IGSS or IDSS in HTGB, do not present a fundamental limitation for eGaN technology to meet and surpass the reliability of standards of MOSFETs and SiC transistors.”

They also commented on the reliability advantages of WLCS packaging, “A conventional power package such as a TO220, LFPAK, or SO8 is needed to protect a silicon-based vertical power device from the environment. EPC’s eGaN FETs chipscale format eliminates the inefficiencies of conventional semiconductor packaging. Package-related parasitic resistance and inductance are eliminated. There are also fewer thermal interfaces that improve the thermal resistance of the eGaN FET compared with comparable MOSFETs.

“Thermal cycling related wearout is a serious reliability concern for power electronics. This is especially true for systems with power saving measures, where components will undergo frequent power-on temperature cycles. Owing to TCE mismatch between the semiconductor and the surrounding package materials, mechanical fatigue accumulates at interfaces over time, leading to cracks and ultimate failure. With lower thermal resistance from junction to board, eGaN FETs experience smaller temperature shifts from power cycling, and therefore have a reliability advantage against thermo-mechanical aging.

“EPC’s efficient chipscale format also greatly simplifies the process of designing for high reliability. With reduced complexity and fewer unknowns, EPC designers can use finite-element simulation to accurately predict and guard-band against common reliability issues. Examples include peak current density and electro-migration, or thermo-mechanical stress in the solder bars. Flip-chip mounting eliminates most of the packaging related reliability problems that have been experienced over the lifetime of the silicon power MOSFET. Wirebonds are gone, along with the issues of lift off and heel cracking. Epoxy delamination is gone. Die cracking experienced during the package molding and trimming process is gone. The designer now has a product with minimum waste and fewer mechanical elements to fail,” the paper concludes.