Hardware Design of Isolated Flying Capacitor Multilevel Converters

To catch up on this series on Isolated Flying Capacitor Multilevel Converters, follow these links:

• Isolated Flying Capacitor Multilevel Converter Basics
• Isolated Flying Capacitor Multilevel Converter Modes of Operation

 

Isolated flying capacitor multilevel converters (FCMLC) are a promising alternative to traditional converters due to their potential for increased efficiency and lower voltage ratings. Hardware design and component selection are necessary criteria for successfully operating the prototypes. As we review the article, we learn the hardware design aspects to consider for all three prototypes.

 

Hardware Design

To ensure safe and dependable testing over the designated 40 V output, components were chosen to consider a wide variety of operations. Both to enable greater voltage testing and to demonstrate how the flying capacitor multilevel converters (FCMFC) may perform more effectively utilizing the same components as the flyback converter, the lower voltage ratings made possible by the flying capacitor structure are not used in this study. This demonstrates that subsequent generations will increase their efficiency further by using semiconductors with lower ratings.

To test the theory of operation previously mentioned, three hardware prototypes were created using identical components, as detailed in Table 1. The two FCMFCs will be compared using the flyback converter as a baseline. The flyback configuration is regarded as an N2 FCMFC. The N3 and N4 converters developed contain 2 and 3 capacitor stages on the secondary, respectively.

Table 1. Component List

Component	Brand	Part Number
Planar Transformer	Coilcraft	NA5871-AL 42 H, 3:5
Flying Capacitor	TDK AVX	CGA6M2X7R2A105K200AA - 1 F 22201C106MAT2A - 10 F X7R, 100 V
MOSFETs	Infineon	IPD30N10S3L-34 100 V, 30 A
Diodes	Diodes Inc.	PDS5100 100 V, 5 A
Bootstrap Diode	Nexperia	PMEG10010ELR 100 V, 1 A, 50 Apk, 3.7 ns
Gate Driver	Texas Instruments	UCC27512
Isolated Gate Driver	Texas Instruments	UCC21220A
Isolated Power	Analog Devices	LTM8067
Controller	Texas Instruments	C2000F28335

 

Control Sensing

The phase-shifted pulse width modulation (PSPWM) control signals for the primary FET and the floating FETs for the flying capacitors on the converter secondary were sent by a Texas Instruments C2000 F28335 Delfino control development board. The board was programmed by PLEC's coder. The primary FET was set up with a soft start function to slowly turn on the double-wound inductor and avoid a high inrush current caused by the uncharged output capacitance. This plan prevents magnetic saturation and protects future versions using FETs with lower voltage ratings. Open-loop control was used to run the FETs at a fixed duty cycle for each testing trial.

 

Isolated Auxiliary Power, Floating Gate Drive, Bootstraps

Floating voltages at the source nodes of the transistors are a problem in multilevel structures. In the case of the FCMFC, this problem is made worse by the need to keep the primary and secondary circuits electrically separate. Luckily, FCMFC does not need advanced bootstrapping techniques. An LTM8067 isolated power chip from Analog Devices was chosen to give the bootstrap circuitry extra power. This chip was set to boost the 5 V supply to 8 V and drive the MOSFETs on the secondary side.

This chip is a flyback converter, so it keeps the primary-to-secondary isolation for the main converter with a 2 kV rating. It has a voltage output that can be tuned with a resistor to drive FETs at higher voltages if needed. For this work, 8 V and 12 V can be used on Infineon FETs, which only handle a 20 V gate drive. For good voltage regulation, the capacitances at the input and output are 2 F and 30 F, respectively.

A 20 m resistor was put in series with the input of the auxiliary converter to prevent a possible resonant tank circuit between the inductance of the supply and the input capacitance. The floating voltage nodes were used as a virtual ground by choosing Texas Instruments UCC21220A isolated gate driver chips. They also have a 4 kV isolation between the logic level controller input side and the secondary high voltage side that drives the flying capacitor MOSFETs.

A bootstrap is required for each floating voltage node, which is the same as a flying capacitor. The N3 FCMFC has one bootstrap circuit, while the N4 converter has two. A resistor (RB), a diode (DB), and a capacitor (CB) make up each bootstrap circuit. An isolated 8 V DC supply feeds the resistor, connected in series to the diode and then the capacitor. The capacitor is then connected to the floating source node, which is the negative side of a flying capacitor C1. This is shown by a red dot in Figure 1 of the bootstrap circuit diagram. 

 

Figure 1. Bootstrap circuit for N3. Image used courtesy of IEEE Open Journal of Power Electronics

 

The positive polarity of CBis hooked up to the isolated driver chip's input voltage node. In this setup, the bootstrap circuit charges the second ground of the transformer using the isolated power supply, and all of the FC network's latter switch(es) turn(s) ON. When the latter switch(es) turn(s) OFF, the voltage across CB is now Viso - VDB + VC1. This lets the voltage between the floating FET gate-to-source be equal to the voltage of the isolated power supply minus the voltage drop across the bootstrap diode.

The bootstrap capacitor is big enough to charge quickly and store enough energy to keep the FET for its required ON-time per cycle. For higher-level converters, like the N4 in this work, the first bootstrap capacitor (closest to the coil) will have to charge through multiple FETs. The PSPWM needs to be set up so that the bootstrap capacitor has enough time to charge. When changing the switching frequency, as in this work, the bootstrap circuit's charging and discharging times must be balanced.

The reverse recovery time of the chosen bootstrap diode is 3.7 ns, which is less than the effective turn-on time of the FET. This is done so that too much current does not damage the auxiliary power supply. The FETs' effective turn-on time includes the time it takes for the drain-to-source voltage to drop after the gate has been charged and the time it takes for the drain-to-source voltage to start dropping when the gate voltage starts to rise.

The bootstrap diode was chosen to handle the highest average current when the capacitor is being charged, which happens when the primary duty cycle is at its lowest, 50%. The diode can handle the peak current during startup, which is the supply voltage minus the voltage drop of the diode divided by the bootstrap resistance, which is about 2 A.

 

Printed Circuit Board Layout and Capacitor Design

In Figure 2, the inputs to the three converters are on the left, and the outputs are on the right. The three converters are all on one 4-layer PCB. From the top to the bottom, it is N4, N3, and N2 (flyback). The yellow wires are 14 AWG current jumpers for a current transformer testing probe that measures primary and secondary currents. There is no electrical connection between the three converters. Each active device got RC pads for snubber circuitry. Based on the analysis, the flying and output capacitors were chosen to be between 20-30 F to get a ripple of 2.5 %. More pads (1 F and 10 F) were added to fine-tune the capacitance based on how well the device worked and experimentation.

 

Figure 2. Printed circuit boards N2 (bottom), N3 (middle), and N4 (top). Image used courtesy of IEEE Open Journal of Power Electronics

 

Snubber Circuits

There are two snubber circuits in the primary FET. The zener snubber circuit stops the voltage from going too high at the switching node, which increases due to leakage inductance energy present at turn OFF. To protect the FET, the zener is set to 27 V. Figure 3 shows that the zener clamp snubs the voltage up to a maximum of 32.03 V before it levels off at the regulated voltage, which is well below the 100 V FET rating. The scale for the voltage is 5 V/div, and the time scale is 2 s/div. The primary FET and other active devices have RC snubbers in series to reduce voltage ringing. These are made to work in all situations over a wide frequency range. For example, Figure 3 at 500 kHz has very little visible ringing.

 

Figure 3. Primary FET switching node voltage with zener snubber clamp. Image used courtesy of IEEE Open Journal of Power Electronics

 

Takeaways of Isolated Flying Capacitor Multilevel Converters Hardware Design

This article has discussed the hardware design of isolated flying capacitor multilevel converters. Some of the takeaways follow.

• The study provides detailed information on hardware design and component selection, including the use of snubber circuitry and fine-tuning capacitance.
• The prototypes were designed to ensure safe and dependable testing over the designated 40 V output, taking a wide variety of operations into account.
• The lower voltage ratings made possible by the flying capacitor structure were not utilized in this study to enable safer testing, but future generations can increase efficiency using semiconductors with lower ratings.
• Isolated flying capacitor multilevel converters have the potential for increased efficiency and lower voltage ratings compared to traditional converters, making them a promising alternative for power electronics applications.
• The N3 and N4 converters developed for this study contain 2 and 3 capacitor stages on the secondary, respectively, demonstrating the potential for increased efficiency through the use of flying capacitor structures.

 

This post is based on an IEEE Open Journal of Power Electronics research article.