Taking Advantage of SiC’s High Switching Speeds


Kevin M. Speer, Ph.D. at Littelfuse Inc.
Xuning Zhang, Ph.D. at Monolith Semiconductor Inc.

Optimizations in measurement, layout, and design is requested

For several years, silicon carbide (SiC) has created a lot of buzz in the power electronics community. At the risk of oversimplifying, the hype comes down to one simple advantage that SiC offers over incumbent silicon power devices: the simultaneous ability to switch at high speeds and block thousands of volts. The result is smaller, lighter systems that are more efficient and often less expensive.

 

For several years, silicon carbide (SiC) has created a lot of buzz in the power electronics community. At the risk of oversimplifying, the hype comes down to one simple advantage that SiC offers over incumbent silicon power devices: the simultaneous ability to switch at high speeds and block thousands of volts. The result is smaller, lighter systems that are more efficient and often less expensive.

However, nothing comes for free. Higher switching speeds present new problems that must not be underestimated, including difficult accurate test and measurement; circuit parasitics that create excessive voltage spikes, EMI non-compliance, and switching losses; and finally, highly sensitive design and integration schemes of the driving and power stages. In this work, we describe some common challenges and illustrate a few best practices that, when properly incorporated, can help users clear these barriers and unleash the myriad benefits of SiC’s high switching speeds.

 

1. Accurate Test & Measurement

 

Challenges

To obtain device performance and establish expectations for how the device should behave in an end application, the importance of proper measurement cannot be overstated. When combined with circuit and

SiC’s ability to switch at very high rates of voltage change (dv/dt) and current change (di/dt) can give rise to four common problems that are illustrated in Figure 1. High dv/dt can produce large transient voltage spikes, as well as common-mode noise seen as damped oscillations. High di/dt generates noise that can couple with current fields in the vicinity. Further, each of these effects can be difficult to measure and diagnose. For this reason, precision measurement tools and accurate test methodologies must be used to uncover problems before they manifest during the prototype stage, product qualification, or worst of all, in the field.

Fig. 1. Turn-OFF waveforms illustrating four typical problems associated with high-speed switching and their measurement
Figure 1. Turn-OFF waveforms illustrating four typical problems associated with high-speed switching and their measurement.

 

Best Practices

Measurement of power devices switching high levels of power at high speeds requires exceptional bandwidth, dynamic range, and minimum stray inductance and capacitance the probes themselves. Tables 1 and 2 show the advantages and disadvantages of various voltage and current measurement methods.

 

Table 1. Voltage measurement methods.

Table 1. Voltage measurement methods

 

For the measurement of voltage, differential probes are commonly used and offer built-in galvanic isolation, but they suffer from limited bandwidth. On the other hand, passive probes and a conventional voltage divider circuit offer suitable bandwidth, but the passive probes require a common measurement reference and lack galvanic isolation, and a voltage divider requires substantial resistor size. Our recommendation is a passive voltage probe because its bandwidth allows the capture of high dv/dt transients.

 

Table 2. Current measurement methods.

Table 2. Current measurement methods

 

There are four commonly used methods for measuring current, none of which is without a drawback. A standard current probe and Rogowski coil may not have an adequate bandwidth for resolving current ringing effects, and the Rogowski coil and current transformer are incapable of capturing dc information. For designs intended only for characterization, the coaxial shunt is recommended due to its large bandwidth and high accuracy, which inherently resolves issues with non-galvanic isolation. Once problems are resolved through design optimization in the prototype, current shunts may be eliminated from the final system.

 

2. Power Loop Layout

 

Challenges

We can treat the power electronics system as consisting of two main circuits: the driver loop (also called the gate-source loop) and the power loop. The power loop contains the load and power semiconductor components. Because this loop switches hundreds of volts and many amperes, the speeds at which voltage and current change (dv/dt and di/dt, respectively) combine with circuit parasitics to produce problems that must be mitigated:

• Voltage spikes at switch turn-OFF events. Due to the multiplication of di/dt and parasitic circuit inductance, these spikes can exceed the maximum voltage rating of the device, leading to catastrophic failure. Due to these limitations, the benefits of SiC may be undermined, as the user must either limit how quickly the devices may be switched, select higher-voltage (i.e., more expensive) components, or resort to multi-level topologies that increase complexity and component count.

• Electromagnetic interference. Due to ringing in the current wave-forms during switching events, induced noise can then couple with other circuit elements. that can lead to inadvertent turn-ON and shoot-through, malfunction of nearby circuits, or non-compliance with mandated electromagnetic compatibility regulations. this ultimately necessitates bulkier, heavier – and more costly! – filter components.

Using a SPICE model for the Littelfuse LSIC1MO120E0080 (1200 V, 80 mOhm SiC MOSFET), the effects of parasitic inductance in a standard double-pulse test circuit were simulated with VDC = 600 V, ID = 20A, Rg = 5 Ω, driving voltage of +20V / -5V, and a di/dt of 2.5A/ns (see Fig. 2). It is seen that the parasitic inductance of the power loop has the most dramatic influence on the voltage spike at turn-OFF, shooting to more than 120% of the DC bus value, even for these modest values of di/dt and Lpwr. 

 

Fig. 2. Simulation of maximum voltage seen from drain to source of the MOSFET in the double-pulse test circuit as a function of parasitic inductance. Note the effect of power loop inductance, Lpwr, giving a spike of more than 100 V above 15 nH at only 2.5 A/ns.

Fig. 2. Simulation of maximum voltage seen from drain to source of the MOSFET in the double-pulse test circuit as a function of parasitic inductance. Note the effect of power loop inductance, Lpwr, giving a spike of more than 100 V above 15nH at only 2.5A/ns.

 

Figure 3 further illustrates the effect of power loop inductance on voltage overshoot. An increase of only 8nH — as much as just the source pin of a TO-247 — can lead to a spike across the device nearly 20 percent higher than the bus.

 

Fig. 3. Simulated VDS waveform at turn-OFF with a parasitic power loop inductance, Lpwr, of 2 nH (green) and 10 nH (blue). A much larger voltage spike is observed, even at modest values of di/dt (2.5 A/ns) and Lpwr.

Fig. 3. Simulated VDS waveform at turn-OFF with a parasitic power loop inductance, Lpwr, of 2nH (green) and 10nH (blue). A much larger voltage spike is observed, even at modest values of di/dt (2.5A/ns) and Lpwr.

 

Best Practices

The most general guideline for optimizing power loop layout emphasizing board compactness and simplicity, with a focus on minimizing the overall loop area. This can dramatically reduce stray inductance, allowing users to utilize the high switching speed made possible by SiC power devices. The next best scenario in a real application is a loop with an outgoing path that overlaps with the return path — a practice known as “lamination.”

As seen in the example board layout illustrated in fugure 4, the dc+ and dc- paths are laminated. Finally, in portions of the loop where lamination is not possible (such as the pins of a through-hole component, for example), power paths should be wide, numerous, and/or cover as little of the two-dimensional space of the board as possible.

 

Fig. 4. An example power board layout, illustrating compactness and optimal lamination of positive (red layer) and negative (blue layer) dc power paths to reduce stray power loop inductance. Sixteen decoupling capacitors are also shown in the center.

Fig. 4. An example power board layout, illustrating compactness and optimal lamination of positive (red layer) and negative (blue layer) dc power paths to reduce stray power loop inductance. Sixteen decoupling capacitors are also shown in the center.

 

Decoupling Capacitors

Another good practice is the use of decoupling capacitors. In the frequency domain, the process of switching at high speeds not only creates higher-order harmonics of the switching frequency, fs, but also peaks related to the transient speeds that extend well into the MHz range.

Typically, the dc link capacitor acts as a notch filter, eliminating oscillations corresponding to fs and its harmonics of appreciable amplitude; however, it does not suppress the megahertz-scale transient-related frequencies, ftrans, which can be highly problematic for coupling into neighboring traces and circuits. To suppress peaks associated with ftrans, one can use relatively high-farad film capacitors connected across the dc link and placed as close as possible to the power transistors’ drain and source terminals to minimize the associated loop inductance.

 

3. Gate Driver Design and Integration

Challenges

The gate drive has two prevailing purposes: to turn on/off the power switches in a stable, well-controlled manner and to incorporate intelligent power system protection. Without proper design layout and inte-gration of the gate drive with the power stage, these objectives can be difficult to achieve. Two of the most common challenges include:

• Gate voltage overshoot and ringing. As indicated in Figure 5, in the presence of high gate and source loop inductance, LG and LS, high values of di/dt can lead to overshoots in the voltage seen at the device gate. Oscillations in the gate voltage waveform can indicate inadvertent turn-ON and, thus, potentially catastrophic shoot-through events (not to mention potential device reliability/lifetime concerns).

• Unnecessary increase of switching losses. Even a modest level of common-source inductance, LCSI, will resist fast changes in current and increase switching losses, as shown in Figure6.

 

Figure 5: An example power board layout, illustrating compactness and optimal lamination of positive (blue layer) and negative (red layer) dc power paths to reduce stray power loop inductance. Sixteen decoupling capacitors are also shown in the center.

Figure 5: An example power board layout, illustrating compactness and optimal lamination of positive (blue layer) and negative (red layer) dc power paths to reduce stray power loop inductance. Sixteen decoupling capacitors are also shown in the center.

 

Fig. 6. Simulated drain voltage (top) and drain current (bottom) waveforms with LCSI = 5 nH (blue) and LG = 20 nH (green). As LCSI increases, there is a delay in the fall of VDS and a simultaneous de-crease in di/dt; this results in an increase of switching losses from 266 μJ to 545 μJ.

Fig. 6. Simulated drain voltage (top) and drain current (bottom) waveforms with LCSI = 5 nH (blue) and LG = 20 nH (green). As LCSI increases, there is a delay in the fall of VDS and a simultaneous decrease in di/dt; this results in an increase of switching losses from 266 μJ to 545 μJ.

 

Best Practices

First, to reduce the effect of inductive coupling between the gate and power loops, one should place these two loops in orthogonal planes where possible. Second, as with the optimization of the power loop, the total gate loop area should be minimized through a combination of lamination and shortening path lengths. Finally, to reduce common-source inductance, the gate loop and power loop should be decoupled; this is most easily achieved using packages with a dedicated Kelvin source, such as the four-lead TO-247 or the seven-lead TO-263.

 

4. Benefits and Challenges

This article highlights some of the prevailing challenges associated with the use of SiC and describes several best practices that can help design engineers justify its use in their systems. However, the benefits of this technology can be difficult to realize due to the problems associated with the high switching speeds that high-voltage, majority carrier power devices make possible.

Design engineers need measurement instrumentation optimized for observing the high-speed dynamics that slower silicon IGBTs do not exhibit. Once this capability is in place, the layout and integration of the gate drive and power stage circuits must also be optimized to exploit the high switching speed that SiC power devices allow.

More information: Littelfuse Inc.  •  Monolith Semiconductor Inc.    Source: Bodo's Power Systems, March 2018