# Comparing Power Transistors Operating at High-Temperature (Tj~200ºC)

## Introduction

The relentless demand for increased efficiency and power density in industrial and automotive electrification applications have pushed semiconductor manufacturers to develop devices able to operate at Tj=175oC junction temperatures and recently at Tj=200oC [1-2]. Although Wide Bandgap (WBG) GaN and SiC semiconductors are capable of operation at Tj>500oC [3], constraints in the chip metallization, wire-bonds, die-attach and package encapsulation materials remain preventive factors [4].

Component manufacturers and power electronic system designers must decide on the appropriate technology from the view point of performance, cost, manufacturability, availability, and perhaps most importantly, reliability. Designers must be aware of all intrinsic limitations of a power semiconductor device to identify potential weak links. Some of these may be structural, constructional, or material limitations not readily available from the manufacturers’ datasheet [5].

In this article, we review and benchmark-analyze state-of-the-art power transistors to identify some of the technologies deemed essential to achieve reliable operation at high junction temperatures. This analysis reveals techniques used in reliability-proven high power transistors already in mass production.

## High Temperature Constraints

In switching transistors used in power electronic systems, the maximum junction/channel temperature Tjmax is generally constrained by

• the rise of leakage current,
• thermal runaway when the semiconductor intrinsic temperature (Ti) is exceeded [6],
• thermomechanically induced strain and residual stress due to CTE (Coefficient of Thermal     Expansion) mismatch of materials, especially in wirebond/die metal interface and back-side die attach solder, and
• the package Epoxy Mold Compound (EMC) [7].

Table 1: Relation between rated Vdd and Tjmax

Table-1 shows the relation between the rated maximum drain operating voltage Vdd and the maximum junction temperature for commercial power transistors. It is well known that owing to their low intrinsic temperature, Si transistors cannot operate reliably at Vdd~800V and Tj>125-150oC due to insufficient operating margin during high temperature transients induced by short-circuit events, thus GaN and SiC are the only viable options available above Vdd=1200V and Tj>175oC.

To assess the robustness of commercially available power transistors, we evaluated SiC MOSFET devices encapsulated in TO-247 type package, focusing on STMicro’s SCT30N120 having the highest stated Tjmax=200oC. We benchmarked and compared this device with the ROHM SCH2080KE having Tjmax=175oC.  Since in these devices the package, die-attach, and solder materials limit high temperature operation, we performed a complete set of advanced physical and material analyses. Figure 1 shows the relevant datasheet specs and physical structure (SEM cross-sections) of the evaluated SiC MOSFETs. Both the devices feature a conventional planar gate structure. The main differences are in the metallization, wire-bond, and the package EMC.

Figure 1: Key datasheet specs and physical structure of the evaluated SiC MOSFET devices

### Temperature rise within the die-attach material

The choice of the correct solder die attach material is essential to prevent delamination and void formation during thermal cycles [4]. The expected die-attach temperature, Tb, is estimated from the rated Tjmax; power dissipation, PT; and semiconductor die area, Adie; thickness, ddie; and thermal conductivity, Kdie as

T_b=T_("jmax")-d_("die")/(K_("die")*A_("die"))*P_T

The general criterion for the die attach maximum temperature and the material melting temperature is TDAmax<0.8xTmelt (in Kelvin degrees); this can be written as

T_("melt")>T_("DAmax")/0.8+70

For example, Ag-based die attach melting temperature is Tmelt ~300oC=573K, hence the maximum operating Ag-die attach temperature would be limited to Tb,Ag ~185oC. Typical die attach materials are given in Table 2.

Table 2: Die-attach materials for high Tj

Figure 2: Estimated steady state die-attach temperature Tb based on parameters extracted by physical analysis

We estimated the die attach temperature Tb, for the evaluated transistors based on our physical analysis data. Figure 2 summarizes the results. In the SCT30N120 transistor, rated at Tj=200oC, the solder temperature rises to Tb ~180oC, implying that its melting point must be Tmelt >295oC. Figure 3 shows the EDX analysis results of the back-side metal and the die-attach material. Still, for high Tj devices, PbAgSn-based soft-solder is being used. The Pb-free SnAgCu solder having TDA (Thermodilatometry) melt temperature of 217-228oC, implies not enough margin for 200oC operation. On the other hand, the PbAgSn-based soft-solder used by STMicro’s SCT30N120 discrete SiC MOSFET is reported to have TDA melt temperature in the range of 276-310oC (Sumikin). Pb-free die-attach solder and/or more advanced materials such as Cu-Sn, Ag-Sn Transient Liquid Phase bonding (TLP) and Ag-nano-particles are not utilized, perhaps indicating a need for further development to comply with stringent reliability and manufacturability/environmental requirements.

Figure 3: EDX analysis results of the back-side metal and the die-attach materials used in several power transistors. For high Tj devices, the PbAgSn-based soft-solder is still being used

### Package mold resin

Being in direct contact with the semiconductor, the package EMC must be able to withstand higher junction/channel temperatures without degradation. Use of higher glass transition temperature Tg epoxy resins is necessary.

Figure 4 shows the EDX material analysis results of the package EMC. The low thermal resistance package resin of the Tj=200oC STMicro SiC device uses ZnO, MgO fillers to enhance thermal conductivity. The FeS2 (iron disulfide) content serves as flame retardant.

Fourier Transform Infrared (FTIR) spectroscopy analysis was used to clarify the differences between the EMCs of the evaluated power transistors. The FTIR spectrums of the EMCs are similar. The FTIR footprint shown in Figure 5 identifies a key enhanced molding material composition technology in the STMicro device, one that is not present in other package mold materials. Strong peaks around 980 cm-1 and the 1200 cm-1 wavenumbers in the FTIR spectrum of the SCT30N120 package are observed at the red lines. Comparison to the reference IR spectrum indicates the presence of P=O bond at the 1200cm-1 wavenumber. Further GC-MS (Gas Chromatography–Mass Spectrometry) analysis of the cresol novolac-type resin detected tri-methyl benzimidazole and triphenylphosphine (TTP) oxide compounds, the latter corresponding to the 1200cm-1 FTIR peak.

Figure 4: EDX analysis results of the package mold compound. The STM device uses ZnO, MgO to enhance thermal conductivity

Figure 5: FTIR spectra of the mold compound revealing the high Tj enhanced resin composition in the SCT30N120 package

### Bond wires

Use of thick bond wire (= 365 um) is necessary for high current applications: (I) The large diameter wire also helps achieve high pull/shear strength, as illustrated in Figure 6, and it serves as a thermal cycle enhancement. (II) The larger peripheral length of the bonding pads helps reduce current density in the top metallization. This is a countermeasure against electromigration. The SCT30N120 device exploits the large area bond pad complemented with a smooth top metallization, as shown in Figure 1.

Figure 6: Plot of the evaluated bonding shear strength as a function of bond-foot perimeter length. High bond wire pull strength is essential to withstand high number of thermal/power cycles. A trend line is drawn to indicate the strength improvement as bond-foot size increases.

## Conclusion

Physical (structural/material) analysis of high power SiC MOSFETs rated for high temperature operation revealed technologies deemed essential to achieve Tj>175oC. Table 4 summarizes the main structural and material properties of the high temperature-capable SiC MOSFETs.

The EMC of the SCT30N120 200oC-capable TO-247-type SiC MOSFET package was evaluated by EDX, FTIR, and GC-MS analyses. Comparing the cresol novolac-type resin with that of a Tj≤175oC conventional transistor, use of ZnO, MgO fillers and Triphenyl Phosphine performance enhancers were detected. When considering manufacturing variations (e.g., material/chemical composition, processing temperature uniformity), the Pb-based die-attach solder may be subjected to ~180oC, thus leaving little margin relative to the melting temperature.

Table 4: Results of benchmarking of power SiCMOSFETs

The presented analysis results provide information for the system designer on package technology, the intrinsic limitations of the power devices that are complementary to the published datasheets; and it can serve as a basis for reliability/quality assurance evaluation. Moreover, it can be used to further enhance electro-thermal device models or to set the direction for further analysis not yet undertaken.

[1]
K. Shenai, “Future Prospects of Wide Bandgap (WBG) Semiconductor Power Switching Devices,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 248–257, Feb. 2015.
[2]
ST Microelectronics press release, “STMicroelectronics Reveals Advanced Silicon-Carbide Power Devices to Accelerate Automotive Electrification,” May 16, 2016.
[3]
D. J. Spry et al., “Prolonged 500 °C Demonstration of 4H-SiC JFET ICs With Two-Level Interconnect,” IEEE Electron Device Letters, vol. 37, no. 5, pp. 625–628, May. 2016.
[4]
M. Ciappa, “Selected failure mechanisms of modern power modules,” Microelectronics Reliability, no.42, pp.653-667, 2002.
[5]
A. O. Adan et al., “Benchmarking Power Transistors and Power Modules for High- Temperature Operation (Tj~200oC),” Presented at the 2017 IEEE Transportation Electrification Conference and Expo (ITEC).
[6]
J. Baliga, “Fundamentals of Power Semiconductor Devices,” Ed. Springer, 2008.
[7]
D. Hiratsuka et al., “Die-Bonding Material and Sintering Joining Technology for Power Semiconductors Allowing Operation at High Temperatures,” in Toshiba Review, vol. 70, no.11, pp. 46-49, 2015 (in Japanese).