Comparing Power Transistors Operating at High-Temperature (Tj~200ºC): Knowing the Transistors in Designs


Alberto O. Adan, Ph. D., Consultant and Senior Analyst at LTEC Corporation

While weighing potential benefits of SiC transistors to meet challenging design requirements to reduce size, weight, improve reliability, thermal management, you need to assess all constraints of high-temperature operation, some less obvious than others.

 

Introduction

The advancement of technology triggered the increased efficiency and power density in industrial and automotive electrification applications, pushing semiconductor manufacturers to develop devices able to operate at Tj=175oC to Tj=200oC junction temperatures. Exceptions to this include Wide Bandgap (WBG) GaN and SiC semiconductors because they are capable of operating at Tj>500oC. Despite the high junction temperatures, the constraints in the chip metallization, wire-bonds, die-attach, and package encapsulation materials remain preventive factors.

There are a lot of factors to consider when component manufacturers and power electronic system designers decide on the appropriate technology to use. Some of these factors include performance, cost, manufacturability, availability, and perhaps most importantly, reliability. The designers must be aware of all intrinsic limitations of a power semiconductor device in order to identify potential weak links. These may be structural, constructional, or material limitations not readily available from the manufacturers’ datasheet [5].

This article will review and benchmark-analyze state-of-the-art power transistors in order to identify some of the technologies deemed essential in achieving reliable operation at high junction temperatures. The analysis reveals techniques used in reliability-proven high power transistors that are already in mass production.
High-Temperature Constraints

 The maximum junction/channel temperature (Tjmax) of the switching transistors  used in power electronic systems are generally constrained by::

  • The rise of the leakage current,
  • The thermal runaway of the semiconductor intrinsic temperature (Ti),
  • The thermomechanically induced strain and residual stress due to CTE (Coefficient of Thermal Expansion) mismatch of materials, especially in wirebond/die metal interface and back-side die to attach solder, and
  • The type of package epoxy mold compound (EMC) [7].

 

  Vdd [V] Tjmax [°C]
   Si MOSFETs ~100 175
   Si MOSFETs ~600 150
   Si IGBT ~600 175
   SiC MOSFETs 1200 175 - 200

Table 1: Relation between rated Vdd and Tjmax

 

The relation between the rated maximum drain operating voltage Vdd and the maximum junction temperature for commercial power transistors is shown in Table 1.  The Si transistors have a low intrinsic temperature making it unreliable at Vdd~800V and Tj>125-150oC. This is due to the insufficient operating margin during high-temperature transients induced by short-circuiting events, making GaN and SiC the only viable options available above Vdd=1200V and Tj>175oC.

The SiC MOSFET device encapsulated in the TO-247-type package particularly on the STMicro’s SCT30N120 with a Tjmax=200oC is evaluated in order to assess its robustness. We benchmarked and compared this device to the ROHM SCH2080KE with a Tjmax=175oC.  A complete set of advanced physical and material analyses are performed to the device since its package, die-attach, and solder materials have a limit on its high-temperature operation. The relevant datasheet specs and physical structure (SEM cross-sections) of the evaluated SiC MOSFETs are shown in Figure 1. Both the devices feature a conventional planar gate structure. The main differences are in the metallization, wire-bond, and the package EMC.

 

Key datasheet specs and physical structure of the evaluated SiC MOSFET devices

Figure 1: Key datasheet specs and physical structure of the evaluated SiC MOSFET devices

 

Temperature Rise Within the Die-Attach Material

 It is important to use the correct solder dies to prevent delamination and void formation during thermal cycles [4]. The expected die-attach temperature (Tb), is estimated from the rated Tjmax, power dissipation (PT), semiconductor die area (Adie), thickness (ddie), and thermal conductivity (Kdie).

The general criterion for the die attach maximum temperature and the material melting temperature is TDAmax<0.8xTmelt (in Kelvin degrees); this can be written as

For example, Ag-based die attach melting temperature is Tmelt ~300oC=573K, hence the maximum operating Ag-die attach temperature would be limited to Tb,Ag ~185oC. Typical die attach materials are given in Table 2.

 

Die-attach materials for high Tj

Table 2: Die-attach materials for high Tj

Estimated steady-state die-attach temperature Tb based on parameters extracted by physical analysis

Figure 2: Estimated steady-state die-attach temperature Tb based on parameters extracted by physical analysis

 

The result of the back-side metal and the die-attach material EDX analysis is shown in Figure 3. The PbAgSn-based soft-solder is being used for the high Tj device. The Pb-free SnAgCu solder having TDA (Thermodilatometry) melt temperature of 217-228oC  proves that there is not enough margin for 200oC operation. On the other hand, the PbAgSn-based soft-solder used by STMicro’s SCT30N120 discrete SiC MOSFET is reported to have TDA melt temperature in the range of 276-310oC (Sumikin). Pb-free die-attach solder and/or more advanced materials such as Cu-Sn, Ag-Sn Transient Liquid Phase bonding (TLP) and Ag-nano-particles are not utilized, perhaps indicating a need for further development to comply with stringent reliability and manufacturability/environmental requirements.

 

EDX analysis results of the back-side metal and the die-attach materials used in several power transistors. For high Tj devices, the PbAgSn-based soft-solder is still being used

Figure 3: EDX analysis results of the back-side metal and the die-attach materials used in several power transistors. For high Tj devices, the PbAgSn-based soft-solder is still being used

 

The Package Mold Resin  

Being in direct contact with the semiconductor, the package EMC must be able to withstand higher junction/channel temperatures without degradation and the use of higher glass transition temperature Tg epoxy resins is necessary.

Figure 4 shows the EDX material analysis results of the package EMC. The low thermal resistance package resin of the Tj=200oC STMicro SiC device uses ZnO and MgO fillers to enhance thermal conductivity. The FeS2 (iron disulfide) content serves as a flame retardant.

The Fourier Transform Infrared (FTIR) spectroscopy analysis was used to clarify the differences between the EMCs of the evaluated power transistors. The FTIR spectrums of the EMCs are similar. The FTIR footprint shown in Figure 5 identifies a key enhanced molding material composition technology in the STMicro device that is not present in other package mold materials. The Strong peaks around 980 cm-1and the 1200 cm-1 wavenumbers in the FTIR spectrum of the SCT30N120 package are observed at the red lines. Comparison to the reference IR spectrum indicates the presence of P=O bond at the 1200cm-1 wavenumber. Further GC-MS (Gas Chromatography-Mass Spectrometry) analysis of the cresol novolac-type resin detected tri-methyl benzimidazole and triphenylphosphine (TTP) oxide compounds, the latter corresponding to the 1200cm-1 FTIR peak.

 

analysis results of the package mold compound. The STM device uses ZnO, MgO to enhance thermal conductivity

Figure 4:   analysis results of the package mold compound. The STM device uses ZnO, MgO to enhance thermal conductivity

FTIR spectra of the mold compound revealing the high Tj enhanced resin composition in the SCT30N120 package

Figure 5: FTIR spectra of the mold compound revealing the high Tj enhanced resin composition in the SCT30N120 package

 

The Bond Wires

The use of thick bond wire (f = 365 um) is necessary for high current applications: (I) The large diameter wire also helps achieve high pull/shear strength and it serves as a thermal cycle enhancement (see illustration in Figure 6). (II) The larger peripheral length of the bonding pads helps to reduce current density in the top metallization. This is a countermeasure against electromigration. The SCT30N120 device exploits the large area bond pad complemented with a smooth top metallization, as shown in Figure 1.

 

Plot of the evaluated bonding shear strength as a function of bond-foot perimeter length. High bond wire pull strength is essential to withstand a high number of thermal/power cycles. A trend line is drawn to indicate the strength improvement as bond-foot size increases

Figure 6: Plot of the evaluated bonding shear strength as a function of bond-foot perimeter length. High bond wire pull strength is essential to withstand a high number of thermal/power cycles. A trend line is drawn to indicate the strength improvement as bond-foot size increases.

 

The Physical Analysis of High Power SiC MOSFETs

The physical (structural/material) analysis of high power SiC MOSFETs rated for high-temperature operation revealed technologies deemed essential to achieve Tj>175oC. Table 4 summarizes the main structural and material properties of the high temperature-capable SiC MOSFETs.

 

Results of benchmarking of power SiCMOSFETs

Table 4: Results of benchmarking of power SiCMOSFETs

 

The presented analysis results provide information for the system designer on package technology, the intrinsic limitations of the power devices that are complementary to the published datasheets; and it can serve as a basis for reliability/quality assurance evaluation. Moreover, it can be used to further enhance electro-thermal device models or to set the direction for further analysis not yet undertaken.

 

About the Author

Alberto O. Adan, Ph.D., received his degree in electronic engineering from Buenos Aires National University, Argentine, and his Ph.D. degree in electrical engineering from Tohoku University, Japan. He has been involved in semiconductor devices (silicon on insulator, silicon, and wideband gap) and integrated-circuit development in Japan since 1987 and has been granted 40 U.S. patents in this field. He is a consultant and senior analyst at LTEC Corporation, Hyogo, Japan, and a Senior Member of the IEEE.

 

References

  1. K. Shenai, “Future Prospects of Wide Bandgap (WBG) Semiconductor Power Switching Devices,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 248–257, Feb. 2015.
  2. ST Microelectronics press release, “STMicroelectronics Reveals Advanced Silicon-Carbide Power Devices to Accelerate Automotive Electrification,” May 16, 2016.
  3. D. J. Spry et al., “Prolonged 500 °C Demonstration of 4H-SiC JFET ICs With Two-Level Interconnect,” IEEE Electron Device Letters, vol. 37, no. 5, pp. 625–628, May. 2016.
  4. M. Ciappa, “Selected failure mechanisms of modern power modules,” Microelectronics Reliability, no.42, pp.653-667, 2002.
  5. A. O. Adan et al., “Benchmarking Power Transistors and Power Modules for High- Temperature Operation (Tj~200°C),” Presented at the 2017 IEEE Transportation Electrification Conference and Expo (ITEC).
  6. J. Baliga, “Fundamentals of Power Semiconductor Devices,” Ed. Springer, 2008.
  7. D. Hiratsuka et al., “Die-Bonding Material and Sintering Joining Technology for Power Semiconductors Allowing Operation at High Temperatures,” in Toshiba Review, vol. 70, no.11, pp. 46-49, 2015 (in Japanese).

 

More information: LTEC Corporation    Source: Bodo's Power Systems, August 2017