# IGBT/SiC-FET Driver Design Tips to Prevent False Triggering

When designing IGBT or SiC FET bridge circuits, proper design of the gate drive circuitry is at least as important as transistor selection to ensure high reliability

Concern for the environment is a major force behind trends such as renewable energy, smart industry and e-mobility. These in turn are driving greater demands for high-efficiency electric power converters and motor drives. These systems must be extremely reliable, and are often required to operate for lifetimes of up to 10 years or more.

To ensure high reliability, designers will choose very carefully when selecting the power transistors for a circuit such as the H-bridge of an inverter or motor drive. However, for best results, they should pay equal attention to designing and laying out the transistor gate-drive circuitry to prevent false triggering of the transistors, which can allow shoot-through currents. These short circuit currents can shorten the lifetime of transistors or, in the worst case, cause immediate destruction. Other undesirable results can include electromagnetic interference that may prevent equipment from meeting EMC regulations.

False triggering can result from poor management of the currents flowing in the transistor’s parasitic capacitances and inductances, which are shown in figure 1.

Figure 1: Parasitic effects and associated currents can disrupt control of the gate voltage

## Parasitic Capacitances and False Triggering

Consider the flow of charging currents between Creverse and Cinput. If the collector-emitter voltage rises when the transistor is turned off, current flows into Creverse according to the following equation:

I_("Creverse")=C_("Reverse")*((dV_(CE))/(dt))

Referring to figure 1:

I_("Cinput")=I_("Creverse")-I_("Driver")

Hence a charging current flows into Cinput that can charge the parasitic capacitance to a voltage above the gate-emitter threshold voltage, causing the transistor to turn on. Idriver depends on gate resistances, and on the inductance Lgate in dynamic operation. The latter depends on circuit layout and the package used.

The designer can adjust various aspects to try and minimise the possibility of false triggering due to charging current flowing from the Miller capacitance. One solution may be to limit dVCE/dt to flatten the switching ramps and ICreverse curve. One disadvantage of this approach is to increase switching losses as a side-effect. Alternatively, optimising the circuitry to reduce the parasitic inductance Lgate can effectively reduce the voltage rise at the gate. However, a more predictable solution is to apply a negative gate-emitter voltage to widen the safety margin up to the threshold voltage.

## Effects of Parasitic Inductance

False triggering can also result from the effects of parasitic inductances such as Lgate and Lemitter. When switched on, the load current flows through the transistor, and therefore also through Lemitter. If the load current is turned abruptly off, Lemitter causes a negative voltage according to the equation:

-V=L_("Emitter")*((dI)/(dt))

This tends to drive the emitter voltage below GND. When the driver acts to send the gate voltage to GND, the gate-emitter voltage becomes positive and thus can turn the transistor on.

In a bridge circuit, where all low-side transistor emitters are connected to the power ground, the effective Lemitter of each transistor is influenced by the inductances of other transistors and their ground connections. Perfect symmetry is difficult to achieve. Hence some transistors can be more susceptible to false triggering, and predictable performance cannot be guaranteed under all operating conditions.

Circuit inductances should always be minimised by keeping conductors and trace lengths as short as possible. However, by using an isolated gate driver for each transistor, the driver ground can be connected directly to the transistor emitter thereby eliminating the effects of layout inductances. The situation can be improved further by using transistors that provide a Kelvin connection to the emitter. Connecting the driver ground to this Kelvin connection effectively prevents Lemitter from influencing the turn-on behaviour.

In addition, using a gate driver that can apply a negative gate-emitter voltage, i.e beyond simply holding the gate at ground potential, to keep the transistor turned off increases the safety margin between the gate-emitter voltage and the transistor’s threshold voltage. This can be highly effective in preventing false triggering.

## Designing the Driver Circuit

The previous section has shown that the performance of the driver circuit has a major impact on the transistor’s ability to resist false triggering.

When designing with IGBTs, typical gate-threshold voltages specified in transistor data sheets tend to be between +3V and +6V. These can decrease to 1 to 2V with increasing junction temperature. A gate-emitter voltage of +15V is generally accepted as the optimum turn-on voltage to ensure fast switching in commonly encountered operating conditions. As discussed, a negative gate voltage can be used to turn the IGBT off. A voltage of -9V has proved to be safe and effective in practice. Dual isolated DC/DC converters with asymmetric voltages at +15V and -9V are now often used as IGBT drivers.

## Driving SiC FETs

In applications that demand high energy efficiency with small size and low weight, such as high-end industrial equipment, inverters, or electric vehicles, silicon carbide (SiC) MOSFETs are becoming increasingly popular. Ideal turn-on and turn-off voltages for SiC FETs are different to those recommended for IGBTs.

SiC FETs have significantly lower threshold voltages than IGBTs. Moreover, the voltage for a given SiC FET decreases with increasing temperature. Logically this would suggest that a greater negative offset voltage on the gate is needed to turn off the device and prevent false triggering. The threshold voltage decreases over lifetime. If the circuit is operated with a gate-source voltage of -5V, this decrease is typically between 0.2V-0.3V over a lifetime of a thousand hours. After this time the threshold voltage remains stable.

If the gate-source voltage is -10V, the change is around five times greater and the variations between transistors are large. The research found these variations to be so high that some devices were already “normal on” at 0V. Hence to ensure consistent performance over the lifetime of the equipment, designers should not apply gate offset voltage values more negative than -5V when working with SiC FETs.

On the other hand, a positive voltage of +15V, as used with IGBTs, would be theoretically possible. As the threshold voltage is substantially lower than for IGBTs, +15V should ensure reliable switching behaviour in SiC FETs. However, the output characteristics at different gate-source voltages have demonstrated that higher voltages would achieve a substantially lower on-resistance, RDS(ON).  A gate-source voltage of +20V makes the most of a SiC FET’s benefits. Hence a DC/DC converter running at +20V/-5V is a good choice for supplying the driver.

Moreover, the chosen DC/DC converter must also provide high isolation. Typical switching frequencies in the range 10kHz-50kHz for IGBTs, or over 50kHz for SiC FETs, can result in steep ramps that subject the converter’s insulation barrier to repeated large stresses. Insulation that is too tightly dimensioned reduces the long-term reliability of the system.

Converters that are designed specifically to supply power transistor gate drivers, such as the RECOM RKZ1509 for IGBT applications, or RKZ2005 or RxxP22005 for SiC-FET applications, provide asymmetrical voltage outputs and high isolation rated up to 4kV or 5.2kV for the RxxP22005. Figure x and x show how these converters can be used to control IGBT or SiC-FET gate drivers.

Figure 2: IGBT gate driver powered by dual asymmetrical isolated DC/DC converter

Figure 3:  SiC-FET gate driver powered by dual asymmetrical isolated DC/DC converter

## Conclusion

In systems that require a robust and reliable power-transistor bridge, proper design of the transistor gate-driver circuitry is at least as important as selection of the power transistor itself. Asymmetrical turn-on/turn-off voltages, with negative-offset turn-off, are known to be effective, and should be used in conjunction with best layout practice: keeping connections short to minimise inductances, and ideally (when designing an IGBT bridge) connecting the driver ground directly to the transistor emitter via a Kelvin connection.

The driver circuitry must be isolated to allow the driver ground to be connected directly to the transistor. Robust isolation is essential to ensure long-term reliability, both in the driver and in the dual asymmetric DC/DC converter used to power the driver.

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